More new UVVM functionality: Simulation Completion Detection

A new improvement to come early out of the current ESA UVVM project is: Completion Detection.

This brand new functionality will allow your testbench to detect that your simulation is finished – or to wait for that to happen. UVVM has had functional coverage and specification coverage (aka requirements tracking) for several years, and that is great in many ways. They do however not necessarily say anything about whether there are commands pending in your verification components or data pending in your scoreboards. The broadcast of 'await_completion()' has been available for many years, but for Scoreboards, the user has had to check every single one for pending expected data. With the new completion detection mechanism you can check all Scoreboards simultaneously using one single command – and you may even combine this with waiting for all VVCs (Verification components) to complete. This makes it both easier and safer to make good test cases.

We expect this new functionality to be published in June? - together with the new functionality on ' Detection of unexpected interface activity '

Check out various sources of info on UVVM - including an overview of coming webinars and conferences where UVVM is presented.

See ?'New ESA project to extend UVVM even further ' for more information about this new ESA UVVM project.

UVVM is an open-source verification tool developed by the VHDL community and sponsored by leading industry actors.