Methods to reduce Power dissipation in Circuit

Due to increase of rate in frequency,the power dissipation of circuit will increase which will result in increase in leakage,increase of cost,larger space area within a given chip and due to that the overall quality of chip will decrease.

Hence due to that reduction in power is a important factor and for that number of low power techniques has been adopted.

The following are some of the methods to reduce power dissipation:-

1] Clock gating:-

In general two kinds of power dissipation occured,one is static and the other is dynamic in nature.Static power can be negelcted.

In the above circuit,due to switching of states increase of dynamic power dissipation occurs.Dynamic power is the sum of transient power consumption and capacitive load power consumption.This can be reduced using clock gating technique which increases the overall capacitance of the clock tree.

One thing to take care is that clock gating circuits is often prone to glitches and that is why a latch has been introduced in the circuit which will take care of it.

2] Encoding Techniques:-

There are different encoding techniques which should be employed in order to reduce power.

• Proper use of don't care encoding helps in reducing state transitions which ultimately saves power.
• If the number of flip flops are more,number of states will also increase and hence Gray encoding should be used instead of binary encoding wherever applicable.
• LFSR should be used wherever needed in order to reduce power.

3] Frequency Application:-

In a larger subsystem or SOC,there are various components and blocks which should not be required to be run with same frequency.

Components like Processors or interface agents like AXI or AHB can run with higher frequency but lower frequency blocks like APB,SPI can run with low frequency.

So by normalising the frequency and providing different frequencies to different frequency can save a lot of power.

4] Operand Isolation:-

This is one of the most useful technique to reduce power dissipation.

If a circuit states are changing continuously depending on its input but as a designer we need to be concerned with the output once in some clock cycle then we can hold the input by inserting some combinational logic when the output is not being used.This process is known as operand Isolation.

4] SOI:-

SOI stands for Silicon on Insulator which has been used in CMOS circuits and consists of two types of insulators.One is SiO2 and the other one is sapphire and the advantage of these is the reduction of capacitance between source to body and drain to body region.

Another advantage is the reduction in diffusion capacitance which results in lower subthreshold leakage in circuits which in turn saves more power.

There are two kinds of SOI techniques available,one is PDSOI(partially depleted) and the other one is FDSOI(Fully depleted).Although FDSOI helps in reduction of tunnelling currents in CMOS but due to technology constraints PDSOI technique is widely being used.

5] Supply Voltage:-

By controlling the supply voltage (VDD) or by minimising the requirement of supply voltage to a desired extent,the power dissipation within a CMOS Circuit can be minimised.

6] Lowering DIBL:-

In short channel CMOS devices,the source and Drain comes very close to channel region and share the charge among themselves.

As the region near the Drain depletion region tend to increase,it reduces the potential barrier.

This problem is known as Drain Induced Barrier lowering and hence by reducing this,power dissipation within a CMOS Circuit can be reduced.