Metal Contamination in Silicon Wafers: Detection, Rapid Diffusion & Gettering

With growing reuse of 200mm fabs and refurbished fab tools, care must be taken to insure that corroded gas lines in facilities and tools do not contaminate wafers. Metal contamination problems in silicon semiconductors were first noticed by William Shockley, the co-inventor of the transistor back in 1960 (1). Mobile ions like Na and K can degrade gate oxide causing threshold voltage shifts, transition metals (Fe, Ni, Cr, Ti, Sc, Co, Cu, Au…) can cause diode leakage, emitter-collector pipes, lower minority carrier lifetimes and gate oxide defects. These are all reasons why silicon wafers, chemicals and gases must be of such a high purity for use in a cleanroom. This article will focus on transition metals in silicon and explain all the different problems, detection and prevention methods used to control these impurities.

Since the wafers, gases and chemicals are so pure in cleanrooms, where can metal contamination come from? The answer is, the facilities, tooling and equipment used to fabricate and handle the silicon wafers, which are often made from stainless steel (Fe,Ni,Cr) and potentially the films deposited onto the wafers. New equipment, made by established semiconductor equipment suppliers will have the assembly, material selection, welding, filters and cleaning processes under control to reduce significant contamination. Used fab tools, old poorly supported tools, refurbished tools or tools made by start-up companies may not have these factors under control. The same can be said for facilities installation, maintenance and repairs. Used tools that are not shut down and cleaned properly can end up having corroded gas lines, especially for chlorine processes if exposed to humid air. These types of corroded lines can potentially spray metal chlorides onto wafers and the process chambers of fab tools.

If the metal contamination is a particle or film on the surface of the wafer, a wet acid bath or spray process can be used to clean off these contaminants. The most common cleaning solution for this is the RCA clean (2). The wafers are prepared by soaking them in DI water. The first step (called SC-1, where SC stands for Standard Clean) is often performed with a solution of NH4OH (ammonium hydroxide) + H2O2 (hydrogen peroxide) + H2O (water). This treatment results in the formation of a thin silicon dioxide layer (about 100 nm) on the silicon surface, along with a certain degree of metallic contamination (notably iron and other transition metals) that is removed in subsequent oxide etching steps. This is followed by transferring the wafers into a DI water bath. The second step is a short immersion in a 1:50 solution of HF + H2O, in order to remove the thin oxide layer and some fraction of ionic contaminants. The third and last step (called SC-2) is performed with a solution of HCl + H2O2 + H2O. This treatment effectively removes the remaining traces of metallic contaminants. The RCA clean before thermal processes, epitaxial deposition and other high temperature processes is a key fab process step.

Detection of metals can begin with particle monitoring from gas lines and process chambers. Do the particles blowing onto wafers or the interior of process chambers contain metals? Next bare sample wafers, or starting wafers, can be used to check for metal contamination after the processing steps. Defects found on wafers can include particles but also crystalline defects that maybe metal precipitates. Metal precipitates can be revealed by a chemical defect etch, such as the Sirtl or Wright etch (3). Secondary Ion Mass Spectroscopy (SIMS), KEVEX/EDAX/EDX X-ray techniques used with SEMs, Neutron Activation Analysis (NAA), minority carrier lifetime via Deep Level Transient Spectroscopy (DLTS) and therma-wave scans have all been used to identify transition metal contamination in silicon wafers (3,4).

Over most anneal temperature ranges the metal-silicon defect after a chemical defect reveal etch results in small pits, which in high density will produce a hazy wafer surface in areas of high metal concentration. The photo below shows a relatively large, unique copper silicide defect that formed on the opposite side of the silicon wafer after a 1100?C, 30 second anneal and Sirtl etching.

Noncontact minority carrier lifetime measurement can also detect metal contamination. Etching of the wafers is not required for this type of test. These systems often use a Gunn diode to project a microwave beam onto the wafer. This beam is deflected onto a detector. A laser pulse is utilized to generate carriers which affect the intensity of the reflected microwave beam. The minority carrier lifetime is extracted from the decay in the intensity of the reflected microwave beam. Since transition metals are known to reduce minority carrier lifetimes in both the dissolved and precipitated state and metal silicide precipitates disturb surface reflectivity, this method can be used to detect metals in silicon wafers (3-6). The frontside lifetime map below shows that after, backside scratching with 4 metals and an 800?C/30sec anneal, the 4 different metals (Ni top, Co right, Fe bottom, Cu left) reduced the minority carrier lifetime on the front surface of the Si wafer.

Comparisons between the different methods of detecting metal contamination in silicon wafers is shown below for different metals, rapid annealing temperature (RTA) as well as lifetime, defect etching and Therma-wave detection methods. Therma-wave is another nondestructive method that uses a reflected, modulated laser beam. Minority carrier lifetime testing seems the best way to detect contamination of transition metals in (100) and (111) silicon.

Finally, there are in process electrical test devices that can monitor pn junction leakage, gate oxide integrity, emitter-collector shorts or pipes that can serve as a final method of detecting metal related device problems in fully processed silicon wafers and ICs.

Rapid Diffusion of Metals through Silicon Wafers

Diffusion of dopants like boron and phosphorous in silicon occurs substitutionally and takes hours to move or diffuse just a few microns into silicon at 900 to 1200?C. It was noted in the 1980’s and 90’s that transition metals could diffuse through an entire wafer (625-700 microns) in just 30 seconds during rapid thermal annealing at 800 to 1200?C (5). Further analysis found that transition metals can diffuse both substitutionally (slow) and interstitially (fast) in silicon (4). During interstitial diffusion the atoms quickly go in between the silicon lattice atoms. Before this work only hydrogen was known to diffuse interstitially in silicon. Rapid diffusion means that devices can be degraded quickly, even from backside contamination like wafer chucks and susceptors that hold a wafer during processing.

Solid-State Gettering of Metals

Metal contamination has been found to precipitate at defects like grain boundaries and dislocations in silicon crystals and wafers. The backside of wafers has been mechanically ground and coated with a polysilicon layer- with dense grain boundaries to getter metals. CZ grown silicon crystals have high levels of dissolved oxygen which can precipitate in the center of the wafers during thermal heat treatments like oxidation and diffusion steps. Transition metals will precipitate at these Si-Ox nanocrystal precipitates, trapping the metals away from the front surface of the wafer. This is often referred to as intrinsic gettering, intrinsic to the wafer and its preparation. Gettering of transition metals like Ni, Co, Fe, Cu has also been noted during rapid thermal annealing, 800-1200?C for 30 seconds to mechanical damage (scratches), ion damage and polysilicon grains (5). Rapid thermal annealing has also been effective a quenching the wafers so fast that the metal precipitates do not have time to form a device degrading defect.

Discussion

What are the implications of all the device failures related to metal contamination and how fast the metals can diffuse in silicon? Traditional CMOS, BiCMOS and Power wafer fabs have avoided using any transition metals in the frontend near thermal process tools. Old CMOS fabs and tools being retrofitted to run Power devices can be a source of problems. Chlorine lines for epitaxy, plasma etch, furnace clean, etc, can be sources of contamination.  In the 1980’s the possibility of buried silicide runners under epitaxial silicon was discussed for 3D integration, but experiments soon showed that rapidly diffusing metals and precipitates would form stacking faults and other defects in the epitaxial silicon layers as shown below.

Copper filled vias, must be added during the low temperature metalization processing steps. Barrier metals like W and Ti are used to prevent rapid diffusion of copper into silicon and precipitate formation during even these low temperature processes < 500?C.

New MEMS silicon devices often employ unique materials like AlN, AlScN, PZT (Pb-Zr-Ti Oxides)in piezoelectrics, VOx for IR sensor sensors, gas gettering metals like Zr, Ti, Fe (7) in vacuum sealed resonators, wafer bonding sealing metals like Au, Sn, Cu, Ge, Al. Titanium wafers have been used for making some MEMS devices (8,9) and other metals like Kovar and stainless steel have also been used in MEMS devices or for wafer level packaging (10) via bonding to a glass or silicon wafers. Many of these MEMS processes and materials use fast diffusing transition metals (Zr, Ti, V, Sc, Fe) and have resulted in many MEMS devices being segregated from CMOS wafer fabs, most often in dedicated MEMS wafer fabs.

Metal contamination will always be a potential problem in traditional CMOS wafer fabs. Various methods of controlling and detecting metal contamination have been developed. New MEMS devices that employ transition methods will need to be integrated into the backend processes to avoid furnace or epitaxial reactor contamination or be separated using a dedicated metal friendly MEMS fab.

References

1.      A. Goetzberger and W. Shockley, “Metal precipitation on silicon p-n junctions,” J. Appl Physics, Vol.31, p.1821, (1960).

2.      W.Kern, “Hydrogen peroxide solutions for silicon wafer cleaning,” RCA Engineer, Vol. 28(4), p.99 (1983).

3.      D. Sparks and A. Levitan, "A comparison between microwave reflectance, thermal wave modulated reflectance and defect etching for detecting transition metals in silicon," Microelectronics Jor., Vol 23, p.283, (1992).

4.      D. Sparks and M. Dayananda, "Amphoteric diffusion of transition metals in silicon," Atomic Migration and Defects in Materials, ASM, p.179, (1991).

5.      D.Sparks, et al., "Anomalous diffusion and gettering of transition metals in silicon," Appl. Phys. Lett., Vol. 49, p.525, (1986).

6.      D. Sparks and N. Alvi, "Device degrading interactions between silicide films and bulk defects during rapid thermal annealing,” in Rapid Thermal Annealing/CVD and Integrated Processing, MRS, Vol.146, p.167, (1989).

7.      D.Sparks, “Thin film getters: Solid-state vacuum pumps for microsensors and actuators: With MEMS applications the use of thin film getters for vacuum packaging passes the century mark,” Vacuum Technology & Coating, Vol. 11, No.4, pp.44-49 April (2010).

8.      C. O'Mahony, et al., "Titanium as a micromechanical material," Journal of Micromechanics and Microengineering, Vol.12(4), p. 438-443, (2002).

9.      C. Parker et al, Inductively coupled plasma etching of bulk titanium for MEMS applications, J.Electrochem Soc, Vol. 152, p.C675-C683, (2005).

10.  D.Sparks, “Metal-based wafer level and 3D-printed packaging,” Chip-Scale Review, Vol. 22 (4), p.14-17, Jul-Aug, (2018).