Major IC Packages and 3D Types Overview

Electronic component packaging, as chip carrier, plays the role of installation, fixing, sealing, chip protection and enhancing electrothermal performance in chips manufacturing and usage. At the same time, the contacts on the chip are connected to the pins of the package shell with wires, and they are connected to other devices through the wires on the PCB, so as to realize the connection between the internal chip and the external circuit.

The chip must be isolated from the outside to prevent impurities in the air from corroding the chip circuit and causing electrical performance degradation. Moreover, the packaged chip is also easier to install and transport. Since the quality of the packaging directly affects the performance of the chip itself, packaging technology is very important for CPUs and other LSI integrated circuits.

The type of package can be roughly divided into two types: dual in-line packaging and surface-mount packaging. In terms of structure, the packaging has experienced the earliest transistor TO (such as TO-89, TO92) packaging and developed to DIP, and then the SOP (small-outline package) was developed by Philip.With the time went by, there are SOJ (J-type packaging) TSOP (thin small outline package), VSOP (very small outline package), SSOP (shrink SOP), TSSOP (thin shrink SOP) and SOT (small outline transistor), SOIC (small outline integrated circuits), etc. As for packaging material, include metals, ceramics, and plastics, in addition, many circuits that require high-intensity working conditions, like military and aerospace grades, are still metal packages.

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Main Packaging Types in Electronics

There are various types of chip packages, such as DIP, PQFP, TSOP, TSSOP, PGA, BGA, QFP, TQFP, QSOP, SOIC, SOJ, PLCC, WAFERS, etc. Next, let's talk about some mature and popular packages.

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DIP (Dual In-line Package)

DIP is an electronic device package with a rectangular housing and two parallel rows of electrical connecting pins. Most small and medium-sized integrated circuits use it, and the number of pins generally does not exceed 100. And they should insert into a chip socket with a DIP structure. Of course, it can also be directly inserted into a circuit board with the same number of solder holes and geometric arrangement for soldering. When using, special care should be taken to avoid damage to the pins.

DIP package structures include: multi-layer ceramic DIP, single-layer ceramic DIP, lead frame DIP (including glass ceramic sealing type, plastic encapsulation structure type, ceramic low-melting glass encapsulation type), etc.

DIP has the following characteristics:

1) Suitable for through-hole welding on PCB (printed circuit board), and easy to operate.

2) The ratio between the chip size and the package size is large, so the entire volume is also large.

DIP is the most popular plug-in package, and its applications include standard logic ICs, memory and microcomputer circuits. The earliest 4004, 8008, 8086, 8088 and other CPUs all used it, where the two rows of pins can be inserted into the slots on the motherboard or soldered on the motherboard.

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SOP (Small Out-line Package)

SOP is also a very common surface-mount package technology. The pins are drawn out from both sides of the package in a gull-wing shape, and the materials are plastic and ceramic. Later, SOJ (J-pin small outline package), TSOP (thin small outline package), VSOP (very small outline package), SSOP (shrink SOP), TSSOP (thin shrink SOP) and SOT (small outline transistor), SOIC (small outline integrated circuit), etc.

The typical feature of SOP is that many pins are made around the packaged chip. The packaging operation is convenient and the reliability is relatively high. It is one of the current mainstream packages and belongs to the real system-in-package. At present, it is more common to apply to some memory ICs.

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QFP (Quad Flat Package)

The distance between the pins of the CPU chip realized by QFP is very small, the pins are very thin, generally large-scale or very large-scale integrated circuits adopt this package form , the number of pins is generally above 100. Chips packaged in this form must use SMD (surface mount device technology) to solder the chip to the motherboard. Chips installed by SMD do not need to punch holes on the motherboard, and generally have designed solder joints for corresponding pins on the surface of the motherboard. Align the pins of the chip with the corresponding solder joints, and then the soldering with the main board can be realized.

Has the following characteristics:

1) This technology is easy to operate and highly reliable.

2) The package size is small, and the parasitic parameters are reduced, which is suitable for high-frequency applications.

3) This technology is mainly suitable for installing wiring on PCB that belongs to surface-mount technology.

At present, QFP/PFP is widely used, and many MCU chips use this package.

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QFN (Quad Flat No-lead Package)

QFN is a quad flat package technology without leads. It has peripheral terminal pads and an exposed die pad for mechanical and thermal integrity. The package shape can be square or rectangular, and there are electrode contacts on the four sides. Since there are no pins, the size is smaller than that of QFP, and the height is also lower than it.

QFN has the following characteristics:

1) Surface mount package, no lead design.

2) It occupies a smaller PCB area without pins.

3) The components are very thin (<1mm), which can meet the applications with strict space requirements.

4) Very low impedance and self-inductance, suitable for high-speed or microwave applications.

5) It has excellent thermal performance, mainly because there is a large area of heat dissipation pad at the bottom.

6) Light weight, suitable for portable applications.

It can be seen from the above, QFN can be used in portable consumer electronics such as notebook computers, digital cameras, personal digital assistants (PDAs), mobile phones, and MP3 players. Considering factors such as cost and volume, QFN will be a growth point in the next few years, and its development prospects are extremely well.

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BGA (Ball Grid Array Package)

BGA technology has become the best choice for high-density, high-performance, multi-pin packaging IC chips. However, the BGA package occupies a relatively large area of the substrate. Although the pins of BGA increases, the distance between them is much larger than that of QFP, which improves assembly yield. Moreover, the technology adopts the controllable collapse chip welding method, which can improve its electrothermal performance. In addition, BGA can be assembled by coplanar welding, which can greatly improve the reliability, and the CPU signal transmission delay realized by this technology is small, so the adaptation frequency can be greatly improved.

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PQFP (Plastic Quad Flat Package)

PQFP is a type of QFP, with leads extending from all four sides of the package body. The distance between the pins is very small. Because the pins are very thin, large-scale or super large-scale integrated circuits over 100 pins adopt PGFP.

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CSP (Chip Size Package)

CSP is a surface mountable package, and is not larger than 1.5 times the area of the die or no more than 1.2 times the width or length of the die. It reduces the size of the chip package outline, so that the size of the package can be as large as the die.

CSP can be divided into four categories:

1) Lead Frame Type (traditional): major manufacturers include Fujitsu, Hitachi, Rohm, Goldstar, etc.

2) Rigid Interposer Type: major manufacturers include Motorola, Sony, Toshiba, Panasonic, etc.

3) Flexible Interposer Type: the most famous is Tessera's microBGA, and also the CTS's sim-BGA is. Other manufacturers represented include General Electric (GE) and NEC.

4) Wafer Level Package: Different from the traditional packaging method, WLCSP cuts the entire wafer into individual chips. It claims to be the future mainstream of packaging technology. The leading manufacturers include FCT, Aptos, Casio, EPIC, Fujitsu, Mitsubishi Electronics, etc.

CSP is suitable for ICs with a few pins, such as memory sticks and portable electronic products. In the future, it will be widely used in information appliances (IA), digital TV (DTV), e-book, wireless network WLAN, ADSL/mobile phones, Bluetooth and other emerging products.

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CLCC (Ceramic Leaded Chip Carrier)

CLCC is a square or rectangular surface-mount ceramic package that has no leads. The ones with windows are used to package ultraviolet erasable EPROMs and microcomputer circuits with EPROMs. This package is also known as QFJ, QFJ-G.

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PLCC (Plastic Leaded Chip Carrier)

PLCC is a plastic package carrier with leads, which is a reduced cost evolution of the ceramic leadless chip carrier (CLCC). It belongs to the surface mount type, and its pins are led out from the four sides, but the external dimension is much smaller than that of the DIP. As for market, PLCC is suitable for installing and wiring on the PCB with surface-mount technology, and has the advantages of small size and high reliability.

PLCC is a kind of patch package. The pins are bent inward at the bottom of the chip, so they are not visible in the top view of the chip. PLCC adopts the reflow soldering process, which requires special equipment, and it is very troublesome to remove the chip during debugging. In short, PLCC is rarely used now.

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Flip Chip

Flip chip, also known as direct chip attach, or its abbreviation, C4, is the process whereby a semiconductor die is attached bond pad side down to a substrate or carrier. It is mainly used in high-end devices and high-density packaging fields. Of all surface-mount technologies, flip chip enables the smallest and thinnest size.

Since the I/O terminals (solder balls) are distributed on the entire chip surface, Flip chip has reached its peak in terms of packaging density and processing speed. In particular, it can be processed by means similar to SMT, so it is the ultimate direction of chip packages and high-density installation.

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Package Test

1) Temperature cycling test (TCT): Expose the package body in a hot air and a cold air in turn, which is to test the ability of the package to resist temperature differences.

2) Thermal shock test (TST): It is to test the thermal shock resistance by exposing the package carrier to the conversion environment of high and low temperature liquid.

3) High temperature storage test (HTST): By exposing the package body to a high-temperature nitrogen furnace at 150°C for a long time, to test the circuit continuity.

4) Pressure cooker test (PCT): Commonly known as the pressure cooker test, it mainly tests the ability of packaged products to resist environmental humidity, and you can shortens the test time by increasing the pressure.

5) High accelerated temperature and humidity stress test (HAST): By testing the anti-humidity ability of the package body in an environment of high temperature, high humidity and bias voltage.

6) Precondition Test (PT): It is a reliability test for the final product after the package is completed. There are tests similar to TCT and THT throughout the mock test. Before the test, confirm product performance, and then start the test of various harsh environments. The first is TCT, to simulate the temperature change during transportation, the purpose is to understand the moisture absorption of electronic components, and then place chips in a constant temperature environment, and finally the soldering process is simulated in the latter stage, to check the electrical characteristics and internal structure of the components.

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Package Purpose

The purpose of packaging is to ensure that the chip has strong mechanical performance, good electrical performance and well heat dissipation after packaging. The main functions are as follows:

1) transfer power

2) transmit electrical signals

3) have heat dissipation

4) play a role of circuit protection

5) make system integration

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Development of Package Technology

Package Trends

Throughout the development of packaging technology in electronics, its trends are mainly reflected in the following aspects:

① Single-chip to multi-chip development

② From 2D to 3D

③ Integration is getting more and more higher.

④ Wafer level develops to board level with larger area. It requires miniaturization, reliability and stability in complex environments, high integration, high-density, multi-pins, low cost, eco-friendly materials, etc.

New-type Package

With the rapid development of technology, the emerging fields such as 5G communications, artificial intelligence (AI), and the Internet of Things (IoT), as well as the upgrade and iteration of traditional fields, have put forward higher requirements for the performance and size of electronic products. For IC manufacturers, new packaging is necessary.

a. System in Package (SiP)

SiP is a method used for bundling multiple integrated circuits (ICs) and passive components into a single package, which enclosed in one or more chip carrier packages that may be stacked using package on package. For example, the memory, interface circuit and processor in a mobile terminal are all packaged in one package to realize the miniaturization of electronics. What’s more, it can realize horizontal and vertical integration of multiple chips from different sources and materials, and can realize high density, which further improve product performance and reduce power consumption. As shown in the figure below:

1) SiP vs SOC

Compared with SiP, I have to say SoC (system on chip), which is a highly integrated chip product. SoC is very similar to SiP, both of which integrate a system including logic components, memory components, and even passive components into one unit. SoC starts from the design point of view and highly integrates the components required by the system onto a chip, where SiP is a way of packaging different chips side by side or stacking chip carriers.

In terms of integration, in general, SoC only integrates logic systems such as AP, while SiP integrates AP, DDR, and SDRAM. In addition, SiP is not use a circuit board or carrier board as a base for chip connection, which can solve the problem of the carrier itself and overcome the board limits.

2) Classifications

The initial SiP mainly designed the distributed structure of multiple chips on a 2D plane, and realized integration through the carrier board. From the above mentioned, 2D SiP is still relatively unable to meet the requirements of the consumers in terms of volume, operating efficiency and power consumption. To meet the needs of high-end electronic products, some chips are arranged in a 2D plane to a 3D stacking method. This is a relatively advanced SiP method at present, called a 2.5D SiP. As shown in the figure below:

The CPU/GPU/SoC and DRAM are stacked and integrated vertically through 3D packaging. Its package area is smaller than the 2.5D packaging, and the TSV interposer part is also removed on the basis of the 2.5D packaging. As shown below:

It can be expected that the multi-chip 3D stacking SiP technology will further shorten the interconnection line distance and further improve the integration level.

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b. 2.5D Package

2.5D refers to that the chips are arranged in parallel on the same substrate, and then connected to the inter-poser through wire bonding, flip-chip or through-silicon vias (TSV). It is mainly divided into the following three steps:

1) Form 3D-DRAM chip integration

2) Form Si-Interposer

3. Integrate the 3D-DRAM chip and CPU/GPU/SoC chip with Si-Inter-poser.

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c. 3D Package

TSV is a high-density 3D chip stacking technology, which interconnects multi-layer chips through silicon vias. It uses the low-cost, high-yield wire bonding technology that will be used in the field of high-performance, high-density packaging for a long time. So it is currently considered to be the most potential technology for 3D integrated package. TSV mainly completes the vertical electrical interconnection of through-silicon holes by filling conductive substances such as copper, reduces signal delay, capacitance and inductance, to realize low power consumption and high-speed communication of chips.

The following is the main process flow:

1) Hole forming

2) Deposit dielectric layer, seed layer

3) Copper plating

4) CMP thinning

5) Overlay interconnection

TSV is not a simple through-silicon via technology in essence, but a high-level system integration solution that interconnects semiconductor die and wafers at a higher density. For this reason, TSV is an important prerequisite for the realization of 3D chip packaging.

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d. Wafer-level Packaging (WLP)

WLP refers to a process where packaging components are attached to an integrated circuit before the wafer on which they are fabricated is separated into individual circuits. It packages chips in 8-inch or 12-inch wafers, and usually the line width and line spacing can reach 2/2 micron. WLP is to package the chip on a square substrate, which is generally larger than the wafer. Obviously, a substrate with a larger size can hold more chips, for example, a 24×24-inch substrate can hold 11 times as many chips as an 8-inch wafer, because the utilization rate of the square substrate can exceed 95%. Due to the improvement of the production efficiency of board-level packaging, the production cost can be greatly reduced by up to 50% when the yield rate is guaranteed to be greater than 90%.

WLP also has the following advantages: better heat dissipation and electrical performance, and does not require interposers, flip chips, filling layers, packaging substrates, etc. Because of smaller size, so it is more competitive.

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Conclusion

In short, packaging technology is an interdisciplinary and cross-industry comprehensive project, which widely involves many disciplines such as materials, electronics, thermals, mechanics and chemistry, and is an inseparable and important part of the development of microelectronic devices.

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