LTP fsm HDL to RTL ,gate netlist,45ns

This article is about the comparison of rtl from different tools for earlier design level to pulse converter. Please refer the article https://www.dhirubhai.net/pulse/level-to-pulse-converter-manish-meshram/ for more details. It is continuous part of that article only.

Here i took the fsm code of moore m/c and mealy m/c and try to get the rtl from dc synopsys and rc complier from cadence, for check how these tool maps the code into better rtl. The snaps from dc and rc compiler for moore and mealy sequentially.

It is dc generated rtl for moore fsm, looks lots of cell are there, from cell report it is around 15 cells, if you remeber the manual map design for the same tooks only 2 flops and 2 gates for ref i shown below.

its critical path, from dc tool itself.

now from cadence tool rtl comes as similar as this, take a look

but it took less number of cells, only 14 , here looks cadence mapping in better way.

Now same for mealy, what i got is as below.

it shows the critical path, from rtl schematic number of cells are 7

from rc compiler , total cells are 5, here also cadence is little better rtl mapper,

one might wondering, tcl script or technology i may set wrong which result in diff cell number, but i used same technology for all rtl transfer and same hdl code, with all proper setting of optimization. hope you get what i mean. Please do comment, like. I will bring similar articles for you.