Logic Equivalence Check (LEC)

A logic equivalence check is a crucial step in the VLSI physical design flow that ensures the gate-level netlist produced during the RTL synthesis is functionally equivalent to the original RTL description.

This verification step is essential to confirm that the optimization and synthesis processes did not introduce any errors or unintended changes in the design's functionality.

It ensures that the logical behavior of the two representations is identical for all possible input combinations.

Purpose of Logic Equivalence Check

?The primary purpose pf LEC is to verify that two different representations of a digital circuit are functionally equivalent. Specifically, it compares the behavior of the original RTL description of the circuit with the gate-level netlist generated after RTL synthesis.

?Functional Verification: The primary and most fundamental purpose of the logic equivalence check is to ensure that the functionality of the circuit remains consistent throughout the design process. It verifies that the gate-level netlist produced during RTL synthesis performs the same logical operations and produces the same output as the original RTL description.

?Detecting Synthesis Errors: RTL synthesis is a complex process involving various optimizations and transformations. Errors or unintended changes can occur during synthesis, potentially altering the functionality of the circuit. The logic equivalence check acts as a quality control mechanism to detect and highlight any discrepancies between the RTL description and the synthesized netlist.

?Optimization Validation: During RTL synthesis, the design often undergoes optimization steps, such as logic minimization, retiming, and technology mapping. While these optimizations aim to improve factors like area, power, and timing, they should not alter the intended functionality of the circuit. The logic equivalence check ensures that the optimizations are applied correctly and do not compromise functional correctness.

?Compliance with Design Specifications: Integrated circuits are designed to meet specific functional requirements and adhere to design specifications. The logic equivalence check helps verify that the final gate-level design complies with these requirements, ensuring that the chip behaves as expected in its target application.

?Error Prevention Downstream: Identifying and rectifying discrepancies at the logic equivalence check stage is critical for preventing errors from propagating further downstream in the design flow. Errors that go undetected at this stage could lead to costly and time-consuming design rework in later phases, such as physical design and manufacturing.

?Formal Verification: In some cases, the logic equivalence check employs formal verification techniques to rigorously prove that the RTL description and the synthesized netlist are indeed functionally equivalent. Formal methods use mathematical algorithms to exhaustively analyze all possible input combinations, providing a high level of confidence in correctness.

?Reducing Risk and Liability: In safety-critical applications like automotive, aerospace, and medical devices, any functional errors in the final chip can have severe consequences. The logic equivalence check helps mitigate the risk of these errors, reducing liability for the chip manufacturer.

?Design Iteration and Debugging: If discrepancies are found during the logic equivalence check, designers can use the results to debug and correct the issues promptly. This iterative process ensures that the design is thoroughly tested and refined, leading to a more reliable and robust end product.

?ECO (Engineering Change Order): Engineering Change Order or ECO in VLSI is used to accommodate last-minute design revisions. ECO is widely used in the industry since it saves money and time. When we talk about ECOs in VLSI, we’re referring to ECOs in the layout. So, on the gate level netlist, you usually start with an ECO. Before passing it on to the layout, the designer must alter the gate-level netlist, make the identical changes in RTL, and then pass all verifications. Before you start changing your layout, make sure the ECO in VLSI physical design passes formal and functional verification.