linux build Variables obj-m and -objs

In the Linux kernel build system, the variables obj-m and -objs are integral to compiling loadable kernel modules. These variables are part of the kernel's build system conventions and are not standard Makefile syntax. They are recognized and processed by the kernel's build infrastructure, known as kbuild.

Understanding obj-m:

• Purpose: The obj-m variable specifies the object files that should be compiled into loadable kernel modules. Each entry in obj-m corresponds to a module to be built.
• Usage: To include a module named mymodule, you would add the following line to your Makefile:

obj-m += mymodule.o
        

• This line tells the build system to compile mymodule.c into mymodule.o and then link it into a loadable kernel module named mymodule.ko.

Understanding -objs:

• Purpose: The -objs variable lists the object files that make up a particular module. This is especially useful when a module consists of multiple source files.
• Usage: For a module mymodule composed of file1.c and file2.c, you would define:

mymodule-objs := file1.o file2.o
        

• This line specifies that file1.o and file2.o are the object files to be included in mymodule.o.

How They Work Together:

When both variables are used, the build system understands that mymodule.o is composed of file1.o and file2.o, and it compiles and links them accordingly to produce mymodule.ko.

Example Makefile:

obj-m += mymodule.o
mymodule-objs := file1.o file2.o

all:
	make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules

clean:
	make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
        

In this example:

• obj-m += mymodule.o specifies that mymodule.o is a module to be built.
• mymodule-objs := file1.o file2.o lists the object files that make up mymodule.o.
• The all and clean targets invoke the kernel's build system to compile and clean the module, respectively.
• all: make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules

all: Target: This is a standard target name in Makefiles, indicating the default goal when no specific targets are given to make. Here, it tells make what to do when you run make without specifying a target.

make Command: Invokes the GNU Make utility.

-C directory Option: Changes to the specified directory before reading the makefiles or doing anything else. /lib/modules/$(shell uname -r)/build typically points to the kernel source tree corresponding to the currently running kernel version.

$(shell uname -r): Uses the shell function to execute the uname -r command, which returns the version of the currently running kernel. This ensures compatibility with the current kernel.

M=$(PWD): Specifies the path of the current directory ($(PWD) is an environment variable that holds the full path of the current working directory). It tells the kernel's build system where to find the module source code.

modules Target: Tells the kernel's build system to compile the module(s) specified by obj-m.

.clean:

clean: Target: Defines how to clean up generated files. Running make clean executes this target.

Are These Fixed Syntaxes or Rules of Make?

No, obj-m and -objs are not standard Makefile variables; they are specific to the kernel's build system, kbuild. The kernel's build system uses these conventions to manage the compilation of kernel modules. They are not part of standard Makefile syntax and are not recognized by standard Make utilities outside the kernel build environment.

For more detailed information, you can refer to the Linux Kernel documentation on building external modules.