Lets learn about Memories:
Memories impact chip design and optimization. Selecting the right memory can 'make or break' performance and area. Understanding Memories is essential knowledge for RTL, verification, physical design, DFT engineers, and Architects. Let's dive into memory fundamentals and best practices."
Memory Types:
1. SRAM (Static Random Access Memory): Low power, high speed, and low density.
Uses flipflop to store the data/bit.
2. DRAM (Dynamic Random Access Memory): High density, low power, and lower speed.
Uses capacitor to store the data.
3. ROM (Read-Only Memory): Non-volatile, low power, and fixed content.
Memory Configurations:
1. Single-Port (SP): One read/write port, simple and area-efficient.
2. Dual-Port (DP): Two independent read/write ports, useful for concurrent access.
3. Two-Port (2P): Two read-only ports or one read/write port and one read-only port.
4. Multi-Port (MP): More than two ports, for multiple concurrent accesses.
Memory Architecture:
1. Word-Based: Accesses entire word (e.g., 32-bit) in one cycle.
2. Byte-Based: Accesses individual bytes within a word.
3. Column-Based: Optimized for sequential accesses.
Let's talk about PPA (Power, Performance and Area)
Performance:
1. Column Muxing: Multiple column using single sense amplified and IO circuitry using muxes.
- Power: Medium impact (reduces power consumption)
- Performance: Medium impact (affects access time)
- Area: High impact (reduces memory array size)
2. Center Decoder: Decoder have access from center of the array instead of periphery.
- Power: Reduces Power
- Performance: High impact (reduces wire delay and caps), Faster access times, Better signal integrity and noise immunity.
- Area: Increases Area, Medium impact.
3. Banking: Splits row decoder into multiple based on different banks row in bit array.
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- Power: Medium impact (reduces power consumption)
- Performance: High impact (improves access time)
- Area: Medium impact (increases periphery area)
4. Refresh (for DRAM):
- Power: High impact (increases power consumption)
- Performance: Low impact
- Area: Low impact
5. Timing Mode: Lets user dynamically select operating voltage to improve performance parameters e.g. Access Time, minimum period etc.
Power:
1) Dual rail memories:
2) Power Gating:
3) Leakage Control: Lets user select the periphery cells threshold voltage. HVT/SVT for low leakage and LVT/ULVT for faster access time with leakage penalty.
Reliability:
1. Error Correction Code (ECC): Detects and corrects data errors.
2. Redundancy: Spare rows/columns for replacing faulty cells in MBIST.
3. BIST (Built-In Self-Test): On-chip testing for memory faults.
Trade-Offs:
- Performance-Area Trade-Off: Increasing word width or number of ports can improve performance but increases area.
- Power-Performance Trade-Off: Reducing voltage or frequency can decrease power but reduces performance.
- Power-Area Trade-Off: Using dual rail or internally switchable memories can reduce power but increases area.
To optimize memory for ASIC digital design:
1. Choose the right memory type (SRAM, DRAM, or ROM) based on application requirements.
2. Select the optimal memory configuration (single-port, dual-port, etc.) for concurrent access.
3. Configure memory architecture (word-based, byte-based, etc.) for optimal performance.
4. Balance power, performance, and area by adjusting memory parameters.
5. Use Synopsys Memory Compiler to generate optimized memory instances.
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3 周Very informative