Latch-up in CMOS: Prevention Design?Rules
Keywords: latch-up, Complementary Metal-Oxide Semiconductor(CMOS), nMOS, pMOS, PN Junctions, PNPN thyristor, silicon-controlled rectifiers(SRCs), bipolar transistors, N-well, P-well, integrated circuits, guard rings, layout, process, packing density, p-type, n-type.
Understanding Latch-up Model Behaviour in CMOS?Devices
Latch-up refers to an unintended short circuit that can occur in integrated devices such as CMOS(Complementary Metal-Oxide Semiconductor) devices, potentially causing the power supply to be inadvertently connected to the ground (Tomako, 2021).
CMOS devices are known for their switching capability, but latch-up disrupts this function, potentially forcing the device to remain in an undesired state. In such cases, the device may fail to turn off unless the power supply is completely disconnected.
Figure 1. A 3D view of CMOS with a complementary pair of NMOS and PMOS in an n-well process (Arora, Chek & Tan, 2009)
Understanding latch-up is essential for effective CMOS device design, as it helps mitigate its effects and prevent the issues caused by this defect.
What is Latch-up?
Texas Instruments defines latch-up as:
“a condition where a low impedance path is created between a supply pin and ground” (Johnson et al., 2015, p. 2).
Furthermore, it is emphasized that latch-up is triggered by current injection or overvoltage. Once activated, the low impedance path remains even after the triggering condition is no longer present (Johnson et al., 2015, p. 2).
Origin of Latch-up: The Latch-up Model of the CMOS IC?Device
Considering a latch-up model of the CMOS circuit provides a better understanding of this condition. The next section derives a model of the latch-up phenomenon in CMOS circuits to reach a conclusion on what leads to this condition.
The cause of latch-up exists in all junction-isolated or bulk CMOS processes due to parasitic PNPN paths. In the design of CMOS integrated circuits, the complementary combination of nMOS and pMOS transistors determines the functionality of the CMOS device. Additionally, the proximity of the PN junctions formed by the nMOS and pMOS transistors creates inherent parasitic transistors and diodes. These parasitic structures form PNPN thyristors, also called silicon-controlled rectifiers (SCRs) (Johnson et al., 2015, p. 2).
The basic cross-sectional structure of the CMOS circuit in Figure 2reveals parasitic NPN and PNP bipolar transistors that frequently contribute to latch-up. The P+ sources and drains of P-channel MOS devices act as the emitters (and sometimes collectors) of lateral PNP devices, while the N-substrate serves as the base of this device and the collector of a vertical NPN device. The P-well functions as the collector of the PNP and the base of the NPN. The N+ sources and drains of N-channel MOS devices serve as the emitter of the NPN. The substrate is typically connected to Vcc, the most positive circuit voltage, via an N+ diffusion tap, while the P-well is terminated at Gnd, the most negative circuit voltage, through a P+ diffusion.
These power supply connections involve bulk or spreading resistance throughout the substrate and P-well. Under normal conditions, only a small leakage current flows between the substrate and P-well, creating a minimal bias across the bulk due to the resistivity of the material. In this case, the depletion layer formed around the reverse-biased PN junction between the P-well and the substrate supports most of the VCC-Gnd voltage drop. As long as the MOS source and drain junctions remain reverse-biased, CMOS devices operate as expected. However, in the presence of intense ionizing radiation, thermal stress, or overvoltage stress, current may be injected into the PNP emitter-base junction, forward-biasing it and causing current to flow through the substrate and into the P-well. At this stage, the NPN device turns on, increasing the base drive to the PNP. The circuit then enters a regenerative phase, drawing significant current from the external network, which leads to the undesirable consequences of latch-up. Once established, a latch-up site, through the fields generated by the conducting currents, may trigger similar action in other elements of the IC (National Semiconductor Corporation, 1995).
Figure 2: Basic CMOS Inverter Cross Section with Latch-Up Circuit Model (National Semiconductor Corporation, 1995)
Mitigating Latch-up
As previously mentioned, latch-up does not pose a risk if the voltage and current levels applied to the device remain within the absolute maximum ratings. However, when latch-up occurs at the CMOS device level, it has severe consequences for the performance of IC chips. These effects include:
Mitigation of Latch-up: Adoption of IC Design?Rules
Reducing the effects of latch-up in CMOS circuits is crucial, and extensive research has been conducted to address this issue. Proper spacing of transistors, diodes, and capacitors can be achieved through characterization processes and design rules, which help minimize the impact of current or voltage pulses on CMOS devices (Johnson et al., 2015, p. 2).
In practice, a combination of process techniques and layout techniques, such as the appropriate placement of well/substrate taps and guard rings, is used to mitigate latch-up (Sabine, 2015). Increasing the spacing between these components helps reduce latch-up occurrences. However, this method has a constraint?—?larger spacing reduces packing density. To overcome this limitation, optimized design rules and best practices are implemented in integrated circuit design.
领英推荐
Figure 3: Guard ring implementation implemented by an automated layout generation tool. (Sabine, 2015)
A literature of the research paper highlights the importance of spacing and isolation rules in preventing latch-up in CMOS circuits and ensuring their reliability and stability (Ker and Jiang, 2023 ).
Spacing and Isolation for Latch-up Prevention
Proper spacing between NMOS and PMOS transistors reduces parasitic PNPN paths that can lead to latch-up. Isolation techniques, such as deep N-well (DNW) implants, buried layers, and N-epitaxial layers, help prevent unintended current paths.
Use of Guard Rings and Collection Rings:
Guard rings around NMOS and PMOS transistors help absorb injected carriers and prevent latch-up. N-moat rings and p-substrate rings are used to collect stray carriers, reducing the risk of latch-up initiation.
Injector-Victim Formalism:
High-side (HS) and low-side (LS) injectors and victims must be carefully identified and spaced apart to prevent unintentional triggering of latch-up. A wider isolation spacing between these regions helps minimize the risk.
Electrothermal Effects and Overvoltage Protection: Excess heat and overvoltage stress can lead to latch-up; proper spacing reduces these risks. ESD protection structures must be designed with spacing rules to prevent unwanted current conduction.
Automated Verification for Layout Compliance: Modern IC designs use automated spacing verification tools to ensure latch-up prevention during chip layout. Schematic-level planning of spacing rules helps optimize IC design before fabrication.
Over the years, several innovative solutions have been developed to mitigate latch-up. Future discussions will focus on these advancements, including patented solutions that have significantly contributed to reducing latch-up effects in CMOS devices (Parrillo, 1988).
References
Arora, V.K., Chek, D.C.Y. and Tan, M.L.P. (2009) The role of ballistic mobility and saturation velocity in performance evaluation of a nano-CMOS circuit, Proceedings of the IEEE Electro Conference, 978–1–4244–4846–3. Available at: https://doi.org/10.1109/ELECTRO.2009.5441185 (Accessed 29 Jan. 2025).
Johnson, M., Cline, R., Ward, S. and Schichl, J., 2015 Latch-Up. Texas Instruments, White Paper SCAA124–April 2015, p.2. Available at: https://www.ti.com/lit/wp/scaa124/scaa124.pdf?ts=1738176288602&ref_url=https%253A%252F%252Fwww.google.com%252F [Accessed 29 Jan. 2025].
Ker, M-D. and Jiang, Z-H., 2023 Overview on Latch-Up Prevention in CMOS Integrated Circuits by Circuit Solutions. IEEE Journal of the Electron Devices Society. Available at: https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=9998049 [Accessed 29 Jan. 2025].
National Semiconductor Corporation, 1995 Understanding Latch-Up in Advanced CMOS Logic. National Semiconductor, Application Note 600, RRD-B30M75/Printed in U.S.A., February 1995. Available at: https://docs.rs-online.com/b620/0900766b80025187.pdf [Accessed 29 Jan. 2025].
Parrillo, L.C., 1988 Method for preventing latchup in CMOS devices. U.S. Patent №4762802. Available at: https://patents.google.com/patent/US4762802A/en [Accessed 29 Jan. 2025].
Sabine, K., 2015 Latchup Prevention In CMOS. Planet Analog, 14 January. Available at: https://www.planetanalog.com/latchup-and-its-prevention-in-cmos/ [Accessed 29 Jan. 2025].
Tomako, 2021 Latch-up in CMOS circuits: threat or opportunity (part 1). Available at: https://monthly-pulse.com/2021/01/05/latch-up-in-cmos-circuits-threat-or-opportunity-part-1/ [Accessed 29 Jan. 2025].