The key to good FPGA and ASIC development : Design for Overview and Readability

Check out our latest Siemens Partner blog on the most important factors for faster and safer FPGA development.

Quality and development time are critical parameters for FPGA and ASIC developers, but there is significant potential for improvement in most projects. Thus, it is essential to evaluate how to exploit this improvement potential.

Check out this blog on how your architecture is essential to achieve good performance for all the key parameters in the figure to the right above - and thus achieve the best possible FPGA development. In EmLogic this is something we continuously focus on, and we teach all our new designers how to assure this - first of all through a good architecture.

If this is of interest, please check out our courses on either FPGA Design or FPGA Verification (or both). These are held live online 7-10 and 21-25 November respectively (as 4 or 5 half-days+). You can find also find sources for learning more about UVVM.

All the things mentioned for FPGA do of course apply equally well to ASICs.