It's a femtosecond world

I fondly recall working on the first generation of 10Gigabit FPGA SERDES and struggling to accurately capture 10 picoseconds of timing jitter on high speed repetitive sampling oscilloscopes. At that time, advanced microwave transition analyzers could discern timing noise below the 1 picosecond level but that was rarely necessary. Since SERDES on those first FPGAs with high speed serial transceivers displayed a fair amount of inherent noise, clock jitter below 1psec rms was generally irrelevant.

Fast forward a decade and a half and we are in the middle of a computing power boom called the cloud. To keep up, processors' and FPGAs' on-chip and external interconnects must operate faster than ever. Today's SERDES are readily driving serial rates higher than 56Gbps across multiple lanes of traffic and reaching unprecedented overall data transfer rates. Consumer's voracious appetite for bandwidth continues increase.

While clocks with 1 picosecond of rms jitter are widely available, the industry accepts this level of performance only at very modest data rates near 1Gbps. These would be adequate for a lower tier of communications applications. For more advanced hardware that needs to connect at a minimum serial rate of 10Gbps, most hardware engineers will only accept a clock jitter much less than 1 picosecond. Most of today's leading edge network processors, CPUs and FPGAs are well beyond those rates.

The above plot shows the progressively lower jitter performance required as serial data rates exponentially increase. The exact requirement varies by chipset and applications since each SERDES may have unique bandwidths of interest and widely differing clock rates. However, as a general rule of thumb, this curve does seem to hold. It puts us squarely between 100fs and 200fs for many of today's 56Gbps and higher serial data rates.

For the this generation of hardware designers, picoseconds (1 in 10 to the power of 12 seconds) have succumbed to femtoseconds (1 in 10 to the power of 15 seconds). Only that low level of timing noise can produce reliably error free communication at today's speeds. Hardware engineers wrestling with high speed design challenges should have no doubt--it's a femtosecond world.