ISSCC 2023 Highlights

The International Solid-State Circuits Conference (ISSCC) took place from Feb 19th to 23rd in San Francisco, CA. The conference is held every year at the San Francisco Marriott Marquis. This year ISSCC turned 70 years and the theme of the conference was “Building on 70 years of Innovation in Solid-State Circuit Design”. ISSCC is undoubtedly a premier global forum for the presentation of advances in solid-state circuits and systems-on-a-chip (SoC). Due to the pandemic, the conference was held virtually for the last two years, but this year it returned to in-person attendance. This year approx. 2,880 people attended the conference. 60% of attendees were from the semiconductor & system industries and the remaining 40% from academia. Paper acceptance rate was ~30% with most of the submitted papers coming from the Asia region. According to the SIA (Semiconductor Industry Association) global semiconductor revenue totaled $573.5 billion in 2022. In the electronic industry, semiconductors are vital components, and this conference brings together the brightest minds from academia and industry.????????

For undergraduate and graduate students ISSCC offered educational circuit insights forum before the conference. The forum was also live on YouTube and you can check the recording here. The forum covered topics such as "The CMOS Latch", "The Art of Linear Analysis of Analog Circuits", "The basics of Low Noise Amplifiers", and "The basics of Analog-to-Digital Converters".?As part of educational programs, ISSCC also offered twelve 90-minute tutorials, seven advanced circuit design forums and one short course.

The conference kicked off on Monday, Feb 20th with 4 plenary talks from distinguished speakers from industry and academia. You can watch the talks at this link

The first plenary talk, “Innovation for the Next Decade of Compute Efficiency” by Lisa Su, CEO of AMD, focused on how to innovate in high performance computing, which is becoming increasingly ubiquitous. Innovation in this field is only possible with an effective, holistic strategy to improve energy efficiency. In her presentation, Lisa explained that continuing innovations in process technologies, modular chiplet architectures, and advanced packaging are key to achieving zetta-scale performance at a high energy efficiency. In order to overcome energy efficiency challenges, domain-specific architectures will need to be extended in a way that accelerates core algorithms, coupled with the deployment of AI across all aspects of the system, from transistors to software. Other plenary talks explored how mixed-signal integrated circuits (ICs) have shaped the world from past to present, the EU chips act's impact on pan-European innovation partnerships, and how 5G is increasing processing needs exponentially.

The plenary session was followed by 33 sessions of presentations of selected technical papers running through Wednesday, Feb 22nd. ISSCC covers a full spectrum of design approaches in advanced technical areas broadly categorized as: (1) Communication Systems, (2) Analog Systems, (3) Digital Systems, and (4) Innovations including micro-machines and MEMS, imagers, sensors, biomedical devices, as well as forward-looking developments that may take three or more years for commercialization. The advanced wireline links and techniques area that I follow, I see papers primarily falling into two categories; one area is 50Gbps/100Gbps/200Gbps wireline links for MR/LR reach applications using PAM4 ADC or analog based SerDes achieving superior performance and energy efficiency; a second area is the use of single ended signaling for XSR/VR reach wireline links for chiplet D2D applications. High speed data converters play a crucial role in ADC based SerDes design. Machine learning and digital processors are other interesting areas. In this case as well, you have two distinct categories, one devoted to HPC AI processors in the cloud for machine learning training and inference with power budgets between 100 and 400 Watts and one devoted to ML inferencing at the edge (tinyML) with well-defined point applications which can fit within a 1mW power budget for small batteries. The other interesting paper discussed power integrity of large multicore processors for machine learning applications. The paper described Wafer level stacking of high-density capacitors & bonding two wafers (one logic die with 60 billion transistors and other DTC capacitor die with 750uF stacked capacitor) together. By making such large deep trench capacitor available near logic die it improved voltage droops significantly allowing headroom for the supply voltage to be elevated and a 40% increase in clock speed achieving peak performance.?

A panel discussion session was held in the evening, student research previews were shown, and some selected papers were demonstrated using test chips. It was incredible to see the quality of student research previews & papers. The ISSCC is a great place for networking, making new connections, and learning about technological advances taking place in several fields. You can find more info at www.isscc.org

Abhay Dixit is a chip designer by profession and loves to write about technology and leadership. He is passionate about technology, leadership, product development and its impact on society. He is based in San Diego, CA and has been working with Qualcomm Technologies Inc for the past 18 years. In his spare time Abhay likes to volunteer at local elementary schools teaching math & science classes and mentoring high school students. Follow him on Twitter at @abhayconnect