Interrupt handling in RISC-V Architecture

Earlier in our introductory article on RISC-V interrupt handling, we explored the basics of RISC-V architecture, its privilege levels, register set, and control and status registers (CSRs) that are crucial for managing interrupts. In this article, we will take a deep dive into the interrupt handling including different interrupt controllers, how RISC core handles an interrupt along with example ISR implementations.

RISC-V Core Local Interrupt Controller (CLIC)

The RISC-V Core Local Interrupt Controller (CLIC) is a key component for interrupt handling that receives interrupt signals and routes it the hart for processing. The CLIC is responsible for managing the interrupt sources that are local to a specific RISC-V core, including the Local Interrupts that are generated within the RISC-V core, such as timer interrupts or software interrupts as well as the External Interrupts that are generated by external devices or peripherals connected to the RISC-V core.

The CLIC provides a range of features to simplify interrupt handling, including:

• Configurable interrupt priority and levels.
• Support for interrupt masking.
• Mapping the privilege levels and trigger types.
• Support for both direct and vectored interrupt handling.
• Integrated support for hardware threads (HARTs).

With support for up to 4096 interrupts, CLIC forms the basis of RISC-V interrupt handling which is crucial for real-time and embedded applications.

RISC-V Platform-Level Interrupt Controller (PLIC)

While the CLIC manages the local interrupts within a RISC-V core, the RISC-V Platform-Level Interrupt Controller (PLIC) is responsible for handling interrupts that are global to the entire RISC-V platform or system-on-chip (SoC).

The PLIC serves as a centralized interrupt controller, providing the following key features:

Interrupt Prioritization:

The PLIC can prioritize interrupts based on their importance, ensuring that critical interrupts are handled first.

Interrupt Masking:

The PLIC allows for selective masking of interrupts, enabling fine-grained control over the interrupt sources that are handled by the system.

By working in conjunction with the CLIC, the PLIC provides a comprehensive interrupt handling solution for RISC-V-based systems, ensuring efficient and scalable interrupt management across the entire platform.

Interrupt Flow in RISC-V

The interrupt handling flow in RISC-V can be summarized as follows:

• Interrupt Occurs: An interrupt is generated, either by a local source (e.g., timer) or an external source (e.g., peripheral).
• Interrupt Detection: The CLIC or PLIC detects the interrupt and determines its source and priority.
• Interrupt Prioritization: If multiple interrupts are pending, the CLIC or PLIC prioritizes them based on their configured importance.
• Interrupt Dispatch: The CLIC or PLIC dispatches the highest-priority interrupt to the appropriate RISC-V core or HART.
• Interrupt Handling: The interrupted PC is stored on to the mepc register. The RISC-V core or HART enters the appropriate privilege mode (typically M-Mode), sets the CSR. The cause of the trap is stored in the mcause CSR and jumps to the interrupt vector table (stored in mtvec) to execute the Interrupt Service Routine (ISR).
• Interrupt Return: After the ISR has completed, the RISC-V core or HART returns to the previous execution state and resumes normal operation using mret/sret instructions.

Understanding this interrupt flow is crucial for designing and implementing Read more...