Intel says "splitting" fab saves billions of dollars a year, how?

At a recent investor webinar, Intel said that the manufacturing business, including Intel Foundry Services, would report profit and loss/accounting separately. This is said to save Intel billions of dollars a year?

We've talked quite a bit about Intel's IDM 2.0 initiative over the past year. As most of you who follow Intel will know, the core ideas of IDM 2.0 include a more aggressive approach to external foundry services, handing over some chip manufacturing to third-party foundries, and keeping Intel's IDM model intact.

In March last year, we also talked generally about the value Intel's foundry business could bring to Intel, including conversion and reuse of resources from older processes, longer life of existing manufacturing assets, and early achievement of higher capacity output and factory utilisation.

However, the IDM 2.0 framework is still very abstract, for example, what is the value of foundry, especially advanced process foundry or not, besides being more profitable; and what is the practical effect of a certain degree of "independence" of foundry on Intel's chip design. At a webinar for investors not long ago, Intel talked more about the logic of decoupling foundry manufacturing from design to a certain extent, which in our opinion is valuable for understanding Intel's future development.

At the investor webinar, Intel said that the manufacturing business, including Intel Foundry Services, will report profit and loss separately; that is, it will be accounted for separately and not really "split". Intel said that there is still a lot of value in integrating the product and manufacturing businesses, such as internal teamwork, and that internal teams acting as "customer 0" for new processes can reduce the potential risk of process nodes for external partners and facilitate rapid volume increases, so there is no need to simply split the business in two. There is no need to simply split the business into two.

So what is the real value of such a "decoupling" or "internal foundry model"?

From IDM 1.0 to 2.0

It is as if it has become very rare for major market players to stick to IDM in the HPC space, with even Samsung's LSI design and foundry business being divested very far away. IDM in the HPC direction in particular can pose a huge risk, after all, cutting-edge manufacturing processes are not comparable to those of the past, both in terms of difficulty and investment.

However, IDM also has some advantages of its own, for example, for the fabless + foundry model, fabless and foundry are still different companies after all, there will be restrictions on data sharing and other issues; in addition, such as Intel as IDM, from the intuitive point of view, the final price of the chip product has room for cost optimization, profits can also be made higher.

However, Intel gave an expected data, that is, assuming that the current foundry + fabless both constitute the same enterprise, compared to Intel, the gross margin (gross margin) difference can be achieved. The former will have a >20% lead by 2022, which is very different from our "gut" judgement.

Looking at Intel's data, Intel did have a gross margin advantage prior to 14nm, but subsequent scissor forks were formed around 2017, when cutting-edge manufacturing processes shifted to 10nm/7nm, and as Intel fell behind competitors like TSMC in manufacturing processes, more of Intel's problems were revealed, including various inefficient resource The manufacturing process lag was revealed as Intel fell behind competitors like TSMC. The manufacturing process lag seems to be the turning point for the IDM model to turn into a disadvantage.

In a recent analysis, SemiAnalysis states that Intel is using more fab space to achieve the same capacity output due to lower tool utilisation and worse yields. This is a major inefficiency. And Intel's design teams are actually somewhat inefficient: more transistors are needed to achieve similar performance than AMD processors - and more fab resources are always wasted, and higher design costs, before the new architecture is in production. These will be mentioned later.

On the surface, the first issue that needs to be addressed is, of course, that cutting-edge manufacturing process technology has to catch up. That is why Intel has set a target of completing 5 process nodes in 4 years: as far as the recent PowerVia technology phase report is concerned, we think that Intel should be able to catch up with TSMC by 2025 as planned. But solving the technical problems of cutting-edge manufacturing processes alone is actually not enough - otherwise there would be no need to mention anything about IDM 2.0.

Such a climate, including the significant increase in capital intensity of cutting-edge manufacturing processes, the arrival of the chiplet era leading to an increase in the value of many older processes, and the fact that Intel was beginning to lag behind its competitors in cutting-edge manufacturing processes, led Intel to look to IDM 2.0 for a change - focusing on solving IDM inefficiencies.

In the broad framework of IDM 2.0, a more aggressive approach to providing foundry services to the outside world would have been a solution to improve resource utilisation, and the same goes for the chip design part to external foundries. But that's not all.

Some anecdotes of IDM inefficiencies

It seems that in our ideal conceptions, IDM is a harmonious combination of design and manufacturing teams, with the process adapted to the design, and everything should be fine. But in reality, this is often not the case. For example, readers who follow Intel CPU parameters will know the concept of stepping. But the stepping in question is stepping before mass production.

After the chip has been designed, the design is sent to the fab, the design is converted into a photomask for lithography, and a whole bunch of process steps are taken to create a test chip ...... Stepping refers to each iteration: each time the iterated version of the design is sent to the fab, the photomask needs to be rebuilt for the test chip.

According to Intel CFO (Chief Financial Officer) David Zinsner, Intel's design team used to do as many iterations as they wanted. For example, the Sapphaire Rapids chip for data centres is said to have gone through 12 iterations of stepping - in comparison to the similarly positioned Bergamo and Genoa from AMD, which only required 2-3 iterations. There is a significant increase in cost and a delay in time-to-market. This is probably one of the ways in which IDM is "capricious".

SemiAnalysis says they heard a rumour that once an Intel design team sent a design to fab and ran a hot lot to test for bugs before they had done a full simulation first - of course this is just a rumour, the truth is unknown, but it was probably to reflect the low cost of the original IDM 1.0 operating model. 1.0 operating model.

Intel expects to reduce the number of samples and stepping, and the solution is to pay for it - the design and product business units need to pay for such operations so that they can moderate their stepping behaviour. But Intel's design teams are said to have started moving to a more industry-standard approach to design technology years ago, although it may still take time for this process to shift.

For its part, Intel says the change could save between $500 million and $1 billion a year.

The same type of change is also associated with hot lots, for example. Generally, a hot lot is a batch of wafers that are processed by a production tool and then sent to the next tool in turn. The so-called hot lot can be understood as a "jumping the queue" batch, which means that a certain batch of wafers is given priority and processed more quickly.

It is not unusual to have a hot lot for certain new process steps or tools for verification, or to test chips with new designs and technologies. But it is said that previously the design team also arranged the hot lot however they wanted to, without regard to tool utilisation or cost.

It is easy to imagine that running a random hot lot is going to reduce the overall production utilization. Intel believes that such a move could also save $500 million to $1 billion per year.

Another typical cost-saving aspect is in testing, sort and bin. We have previously written about the so-called "binning" process. In addition to the usual reliability and endurance tests, the need for tests such as the "binning process" is based on the fact that there are always yield differences in chip manufacturing, and that for chips such as CPUs and GPUs, which are difficult and expensive to design and manufacture, even if there are problems with the final chip, such as a certain For CPUs and GPUs, which have high design and manufacturing difficulties and costs, even if there are problems with the final chip, such as a certain block not being available or the electrical characteristics not being ideal, they can still be grouped into different SKUs for sale by way of testing and binning.

Intel has highly customized tools and processes for testing, sorting and binning, which may have been technically advantageous. But this time Intel specifically mentioned that compared to its competitors, Intel's testing time would be significantly longer, even 2-3 times longer. From the end result, at least the recent Intel processors do not show much of an advantage in terms of product reliability compared to the competition.

Then directly targeting testing, sorting and binning charges would also allow the corresponding business teams to tighten up their testing strategies and save about another $500 million per year. It does feel like these initiatives are also decoupling design from manufacturing to some extent, significantly improving resource utilisation.

?

De-coupling is more difficult

Another objective drawback of the IDM model in the HPC sector is that it is difficult to trace who is to blame for certain problems in the product, and it is difficult to make the responsibility clear, at least to individual teams and business units. For example, in the case of CPU performance, efficiency and cost, if the figures are not good enough, it can be difficult to find out whose problem it is, given the close integration with the business.

In other words, if the design team is to blame and the architecture is inefficient, then this key issue is likely to be hidden from the whole picture in the original IDM 1.0 model, which is based on an external design client, an 'internal foundry model' and a clearer separation of roles and responsibilities. The final problem is more clearly laid out on the table. At least it is much more difficult for the design team to pass the buck to the manufacturing business.

In fact, in this case, while saving costs, it also somewhat reverses the capriciousness of the design team: if it is more difficult to "dump" and you can't run hot lots, stepping and testing at will, you have to work more on architecture, cost and so on in the early design phase. Intel believes this could result in $1 billion in annual savings, as design teams are more careful to look at whether certain features are worth spending on die size.

SemiAnalysis says that previously Intel design teams would ignore constraints such as lithography throughput and reticle size. This doesn't happen on the side of a foundry dedicated to TSMC, which is the norm for customers.

Finally it's worth mentioning the issue of yield and capacity as a foundry - this is very different from the past when cutting edge manufacturing processes were all geared towards in-house. TSMC's 7nm and 5nm processes are all said to have gone from 0WPM to 50,000WPM (wafers/month) in just 6 months. Intel's previous history, on the other hand, doesn't look so smooth, with Ice Lake and Sapphaire Rapids having slow ramp-ups.

This time Intel has said it will charge an internal "flat wafer price" over the life of the process node in order to accelerate capacity ramp for new products. Although we don't know exactly how this works out financially, Intel has also said that it will save $1 billion per year and increase speed to market.

There's also the fact that as an in-house oriented foundry service, there's also the need to charge for capacity take-up, lock-in orders - Intel says that before this the design team could change forecasts whenever they wanted to... So it seems that the partial decoupling of design and manufacturing is slightly more internal market-oriented. The manufacturing business is no longer as accommodating to the design team as it used to be. Naturally, this also increases tool utilisation for manufacturing, as better production planning can be done both internally and externally.

Based on our observation of Intel's product roadmap, advanced manufacturing processes and advanced packaging technologies are all being thrown out, products other than CPUs are also starting to be fully laid out, and cutting-edge technology research is continuing, so the momentum is still quite good. However, we expect that this year and next year will still be a difficult two years for Intel.

Advanced manufacturing processes are catching up, and processors represented by Core Ultra CPUs are starting to adopt chiplet and advanced packaging technologies across the board, and the level of technology layout is better than that of competitors such as AMD, which is of course very beneficial in the long run; however, we believe that it is difficult to create the absolute advantage in the short term, and it is not easy to break the game now that we are surrounded by strong enemies. But we do not believe that these will create the absolute advantage in the short term.

IDM 2.0 does seem to us to be the key to Intel's "return to the throne" in the medium to long term, and it doesn't matter that Meteor Lake and Sapphaire Rapids won't break the mould, because they are all products that are preparing the ground for the next generation of technology. The next generation of technology is ready to take the lead.