Implementation of Microblaze RISC-V with Zynq PS on Zedboard using Unified Vitis IDE 2024.2

Story

Microblaze has been a trusted workhorse for softcore microprocessor implementation on FPGAs. Microblaze is a 32-bit RISC Harvard architecture microprocessor softcore, which means processor instruction and data are accessible on separate buses. Recently, with the 2024 release of Vivado, Microblaze has been upgraded to RISC-V architecture, providing a free-of-cost gateway to leverage the open-source RISC-V software ecosystem on FPGAs. Zynq, on the other hand, is an All Programmable System-on-Chip (APSOC), which means it has a dual-core ARM cortex A9 microprocessor implemented on silicon fabric along with an Artix-7 equivalent Programmable Logic (PL). The ARM cortex A9 processor can be configured using the Zynq IP provided with Vivado at no extra cost. The ARM processor on the Zynq chip can be used as a primary microprocessor to implement embedded Linux or FreeRTOS, while on the other hand, the MicroBlaze processor can be used to control a peripheral sensor at bare-metal level, providing a leaner parallelised system implementation. With recent changes made in Vitis IDE, making it to transition towards a Visual Studio Code based Unified IDE from the Eclipse based Classical IDE, this article is intended to serve as an entry point for developers trying to leverage the combined performance of PS, PL, and Microblaze V on Zynq 7000 chip with Vitis unified IDE. Zedboard is used as the hardware platform for implementation in this article.

Hardware Development in Vivado 2024.2

Step 1: Create a new project in Vivado.

• Open Vivado, click File -> Project -> New.
• Click 'Next'. In the next window, provide the Project name and Directory path. Make sure to use short paths, as using long paths may result in unintended errors, especially in Vitis unified IDE. A better approach would be to have separate Vivado and Vitis workspace folders on a drive.

• Click 'Next'. In the next window, choose Project Type. Here, we are working on a fixed RTL project. Vitis supports two types of platforms, one of which is extensible in Vitis HLS (useful in developing AI accelerator circuits). The other one is a fixed platform where the hardware platform is completely developed in Vivado and then exported to Vitis IDE for software development. Note that if 'Project is an Extensible Vitis Platform' is selected here, then software run and debug options in Vitis IDE will get disabled. The entire project will have to be rebuilt anew in Vivado if this option is unintentionally clicked.

• Next, select the Default Part. Here, we have a choice of selecting either the chip or the development board. We are choosing the Zedboard as our intended design target. If the intended board or part is not found in the list, you may be required to press the 'Refresh' button to refresh the device catalogue. If this still does not show your device, chances are you are using a custom board; in that case, manually loading the board files might solve the issue. This section of the Vivado manual can be helpful.

• Next, click 'Finish'. This will complete the creation of the project.

Step 2: Add the Block Design

• To add a block design, click Flow Navigator -> IP Integrator -> Create Block Design.
• In the next window, click 'OK'.
• In the next window, add IPs by pressing the plus sign. Add the Zynq7 Processing System IP and Microblaze V IP.

Step 3: Run Block Automation

• Click the 'Run Block Automation'. Select 'processing_system_7_0'. Select default settings. Click 'OK'.

• Next, select 'microblaze_riscv_0'. Keep the following settings and click OK. 1. Preset: None (Presets available are Real-Time and Microcontroller) 2. Local Memory: None (As we are going to use DDR as program memory for Microblaze) 3. Local Memory ECC: None (As no Local Memory is selected) 4. Cache Configuration: 32 kB (higher memory will provide higher performance but consume more BRAM in implementation) 5. Debug Module: Debug Enabled (Connects the Microblaze Debug Module, which enables the JTAG-based debugging of the MicroBlaze processor) 6. Peripheral AXI Port: Enabled (Enables M_AXI_DP port, which allows Microblaze to control peripheral modules) 7. Interrupt Controller: Not selected (Connects Interrupt Controller to Microblaze as this example design does not cover interrupt handling; we are not selecting it) 8. Clock Connection: 100 MHz clock from Zynq7 Processing System

Step 4: Configure Microblaze RISC-V IP

• Double-click the Microblaze RISC-V IP to configure it to work with the Zynq7 Processing System. Here, the Microblaze will work as a secondary processor, and we will wake it up once the boot artefacts for Zynq7 PS and the bitstream file for Zynq7 PL are loaded. Click 'Enable Discrete Ports'. This will give us ports on the Microblaze processor IP to manage processor sleep and wake-up.

• Next, select the 'Advanced' option from the Micrblaze IP top ribbon. This will give us additional configuration options for Microblaze. Here, we will set the 'Vector Base Address' in the 'Interrupt & Reset' section to 0x10000000. This will be the DDR address where Microblaze will look for program instructions once it wakes up. Click OK to finish the Microblaze configuration.

Step 5: Configure Zynq 7 Processing System IP

• Double-click the Zynq IP block and select 'PS-PL Configurations'. First, disable the General Purpose Master AXI port, as we need not configure any peripherals from Zynq PS. Then, enable one General Purpose Slave AXI port, which will allow Microblaze to access UART on the PS side. Lastly, one High-Performance Slave AXI port will be enabled, which will allow the Microblaze Cache Interface to access DDR on the PS side.

• Next, select 'Peripheral I/O Pins' to configure the Zynq IP with the following Input Output pins.

• Next, we enable GPIO EMIO (General Purpose Input Output Extended MIO) pins, which we will use to wake up the Microblaze RISC-V softcore. In 'MIO Configuration', we change the GPIO EMIO size to 1. This will complete the Zynq7 IP configurations.

Step 6: Microblaze Reset_Mode[0:1] and Wakeup[0:1] port connections

• Now, we will add a 'Constant' IP to the Block Design, which we are going to use to set the 'Reset_Mode[0:1]' of Microblaze. The 'Reset_Mode[0:1]' port of Microblaze decides what Microblaze will do once it comes out of the reset mode. The default reset mode (0x00) enables the MicroBlaze to start executing the code from the memory location mentioned in 'Vector Base Address' immediately after coming out of the Reset state. Now, this option is fine if we are using local memory with Microblaze, which, like the Microblaze processor, will get implemented on the PL itself. Thus not relying on Zynq7 PS initialization. However, as we are using the DDR memory location to store Microblaze instructions, this might create a problem. In the Zynq boot sequence, PL needs to be configured before PS, so when Microblaze, which is implemented in PL, come out of reset state and tries to access the DDR address, it will not be able to do so as PS has not been configured yet and DDR on Zedboard is connected to PS side. Thus, it results in a hang state of Microblaze. To avoid this, we will set the reset mode to 0x01, which means the Microblaze will enter a sleep state as soon as it comes out of the reset. And it will wait for any of the bits of 'Wakeup[0:1]' input to go high. When any of the two bits of 'Wakeup[0:1]' go high, Microblaze will come out of the sleep state and start executing the instructions from the 'Vector Base Address' in DDR. Hence, we set the 'Constant' IP width to 2 and the value to 01 and connected it to the 'Reset_Mode[0:1]' port of Microblaze.
• Add one 'Concat' IP to the Block Design and connect the 'Dbg_Wakeup' output port on Microblaze to one of its ports while the 'GPIO_O' output port on Zynq7 PS IP on its other port. Connect the concatenated output of the 'Concat' IP to the 'Wakeup[0:1]' port on Microblaze. This allows us to wake up the Microblaze post reset state from both Zynq7 PS directly or when execution is continued via the 'Debug' port of Microblaze. Here, we have only attempted to wake up Microblaze from Zynq7 PS.
• The connections to the 'Reset_Mode[0:1]' and 'Wakeup[0:1]' ports are shown in Fig. 12.

Step7: Microblaze and Zynq7 PS interconnection

• Next, we add two 'AXI Smartconnect' by clicking on the plus sign for 'Add IP', one for Microblaze Cache and the other for Microblaze Peripherals. As the Microblaze Cache interface has two master AXI interfaces, M_AXI_IC and M_AXI_DC, for instruction and data, respectively, the AXI smartconnect for Microblaze Cache is configured for two master interfaces and one slave interface. In this way, we connect M_AXI_IC and M_AXI_DC through AXI smartconnect to Zynq7 PS High-Performance Port 0, S_AXI_HP0. Similarly, the Microblaze Peripheral interface M_AXI_DP is connected to the Zynq7 PS General Purpose Port 0, S_AXI_GP0 through another AXI smartconnect configured for a single master and slave interface.

Step 8: Reset and Clock interface connection

• Add 'Processor System Reset' IP to the block design. Connect its 'mb_reset' port to the 'Reset' port of Microblaze. Connect its 'ext_reset_in' to the 'FCLK_RESET0_N' port of Zynq7 PS IP. Connect its 'mb_debug_sys_rst' port to the 'Debug_SYS_rst' port of the Microblaze Debug Module. Finally, connect its 'interconnect_aresetn' port to 'aresetn' port of both of the AXI Smartconnect IPs.
• Next, click 'Run Connection Automation' and accept all automation to connect the clock inputs to the IPs. The final block design will look like Fig. 12.

Step 9: Assign Addresses to Slave Segments

• Click on the Address Editor window to assign addresses to different slave segments in the block design. Currently, the Address Map is empty. There is an option to auto-assign the addresses. However, I prefer to assign some of them manually, keeping in mind the design parameters. The final address editor, after assigning the addresses, will look as shown in Fig. 13. Here, the Base Address can be assigned manually by clicking on the pencil sign in the address fields. The High Address will automatically be set based on the range selected.
• First, we auto-assign the address to the GPIO_O enabled on Zynq7 PS by right-clicking on the row and selecting 'Assign'. It comes out to be a Base address of 0xE000_0000 and a High Address of 0xE03F_FFFF with an address range of 4MB.
• Next, we carefully assign the address to GP0_DDR_LOWOCM. This is the section of memory (DDR and/or On-Chip Memory) that the M_AXI_DP port on Microblaze can access via Zynq7 PS Slave AXI General Purpose Port 0 (S_AXI_GP0) alongwith the M_AXI_IC and M_AXI_DC ports on Microblaze via AXI High Performance Port 0 (S_AXI_HP0). So there could be a clash in address assignment.
• Here we kept S_AXI_GP0 memory access limited to 128 MB, ranging from the base address 0x0800_0000 to high address 0x0FFF_FFFF. Although Zedboard has a DDR of 512 MB with base address ranging from 0x0 to 0x1FFF_FFFF, the initial addresses from 0x0000_0000 are reserved for loading boot artefacts; hence, we chose to avoid allocating them to the Microblaze Data interface. Refer to the address map of the Zynq7 Device here to know more about this.
• Lastly, for Microblaze cache interface M_AXI_IC and M_AXI_DC, which are connected to DDR via the S_AXI_HP0 interface, we allocated 256 MB of the possible 512 MBs with base address 0x1000_0000. The base address here is the same as the 'Vector Base Address' given while configuring the Microblaze RISC-V IP. It is advisable to keep them the same.
• This completes the Block Design. We can now 'Validate Design' by pressing F6. This should pass without any error or warning.

Step 10: Generate Bitstream and Export Hardware Design

• First, we 'Generate Block Design' in Flow Navigator -> IP Integrator -> Generate Block Design. Accept the general settings and click 'Generate'.

• Next, create the design wrapper for the block design, which is basically the Verilog/VHDL code with the block design instantiated and port mapped, by right-clicking on the block design in the 'Sources' tab and selecting 'Create HDL Wrapper...'.

• Then click 'Generate Bitstream' in 'Flow Navigator'. Accept default settings, and click 'OK'. It will take some time. Once complete, we should have a 'Bitstream Generation Successful' message.

• Once Bitstream generation is complete, export the design for bare metal application development in Vitis Unified IDE, by clicking File -> Export -> Export Hardware. This should bring you to this screen. Click 'Next'.

• Now, this should bring you to make a choice between including Bitstream and the exported hardware platform. Including bitstream to the exported platform will allow us to load bitstream to the PL side from the VItis IDE itself. Otherwise, we have to program the PL side from Vivado.
• Click 'Next'. Choose the name of the exported file and the location where it should be stored. Click 'Next'. And 'Finish' afterwards. This completes the hardware export of the design.
• The exported file with the .xsa extension is basically a single file that carries all the hardware design data like device addresses, configurations, etc., which will be useful in writing software for it.

Step 11: Launch Vitis IDE

• Next, launch Vitis IDE from Vivado. It's important to do so from the Vivado itself. Opening Vitis independently may create some unexpected errors in Vitis while building projects.
• Go to Tools -> Launch Vitis IDE, to launch Vitis IDE from Vivado.

Software Development in Unified Vitis IDE 2024.2

Step 1: Set Vitis workspace

• First, we create the workspace folder to work on the exported design from Vivado. Click 'Set Workspace' on the Vitis welcome page. This will allow us to select the folder which will act as the Vitis workspace for the project. Please note that it is very important to keep a small directory path in Vitis to avoid unexpected errors while building the project. For this purpose, we chose a small Vitis directory path: D:/Vitis/Zedblaze.

Step 2: Create Platform Project

• Once the workspace is set, create the Platform component. Add component name and location. Click 'Next'.

• Select platform creation flow to 'Hardware Design'. And click 'Browse' to include the Hardware Design (.xsa) exported from Vivado earlier. Click 'Next'.

• Next, we select the OS and Processor. There are three options available here for OS: standalone, freertos, and Linux. As we are working on bare-metal application development, we have chosen 'standalone'. For the processors, we again have three options because we have included a softcore Microblaze RISC-V processor along with a dual-core ARM Cortex A9 processor.
• We are going to choose 'microblaze_riscv' for now. It will create a processor domain for Microblaze over the project platform, in which we can develop bare-metal applications for Microblaze RISC-V. Later, we will create another processor domain for PS7 Cortex A9 on the same platform to develop bare metal application for the ARM processor. This order could be reversed as well without any practical consequence. We also select 'Generate Boot artifacts', which will generate the First Stage Bootloader (FSBL) for the Zynq7 Cortex A9 processor. Click 'Next' and then 'Finish'. This will complete the platform creation.

Step 3: Create an Application Component for Microblaze

• Click on the 'Examples' icon from the vertical ribbon. Select the "Hello World" application component from the list of 'Embedded Software Examples' by clicking on the plus button, as shown in Fig. 22.

• Add the application component name and location. Click 'Next'.

• Select the platform component created earlier in the previous step. Click ' Next'.

• Select the domain 'standalone_microblaze_riscv', which is created by default while creating the platform component, as we have chosen 'microblaze_risc_v' as the processor while creating the platform. Click 'Next' and then 'Finish'. This will complete the creation of the application component for Microblaze RISC-V.

• Here, we change the helloworld.c code to an infinite loop printing a message.

#include "xil_printf.h"
#include "sleep,h"

int main()
{
    while(1){
    xil_printf("Hello from Microblaze\n\r");
    xil_printf("Successfully ran Hello World application on RISC-V\n\r");
    sleep(1);    
    }
    return 0;
}        

Step 4: Create an Application Component for ARM Cortex A9

• Repeat the previous step for creating another 'Hello World" application component. The only exception this time will be the creation of a new domain in addition to the 'standalone_microblaze_riscv'. Select 'standalone_ps7_cortexa9_0' as the 'Name' and 'Display Name' of the new domain, and select 'OS' as 'standalone' and 'Processor' as 'ps7_cortexa9_0'. Click 'Next' and then 'Finish'. This will complete the creation of the application component for ARM Cortex A9.

• Similar to the previous step, change the helloworld.c code to an infinite loop printing a message.

#include "platform.h"
#include "xil_printf.h"
#include "sleep.h"

int main()
{
    init_platform();
    while(1){
    xil_printf("Hello from Zynq7 PS\n\r");
    xil_printf("Successfully ran Hello World application on ARM Cortex A9\n\r");
    sleep(1);    
    }
    cleanup_platform();
    return 0;
}        

Step 5: Build the platform and application components

• Select the application component from the list of 'Vitis Component' and then the 'Build' option in the 'Flow' menu. It will initiate the build operation for the application component, automatically building the platform component first. Once the build is complete, a green tick will appear, indicating the successful build of the component.
• Repeat the same step to build both of the application components.
• Note if the 'Project is an Extensible Vitis Platform' is selected while creating the project in Vivado. Then the 'Run', 'Debug', and 'Create Boot Options' options in the 'Flow' menu will be disabled. The entire project will have to be rebuilt anew in Vivado if that option was unintentionally clicked.

• Take a moment here to look at the linker script file, lscript.ld, for the application component 'hello_blaze'. Observe 'Available Memory Regions'. Here, there are two memory regions, ps7_ddr_1 and ps7_ddr_0, with base addresses 0x1000_0000 and 0x0800_0000, respectively. The size of ps7_ddr_1 is 0x10000000, which is 256 MB, and ps7_ddr_0 is 0x08000000, which is 128 MB. If we see this information in the context of the address map shown in Fig. 13, we can observe that both of these memory sectors are made available by us to the Microblaze, with ps7_ddr_0 connected to Microblaze M_AXI_DP port through Zynq7 PS port S_AXI_GP0 and ps7_ddr_1 connected to the Microblaze cache interface M_AXI_IC and M_AXI_DC ports through Zynq7 PS port S_AXI_HP0. Also, we can see that various linker sections of the Microblaze Processor software system are mapped to ps7_ddr_1, indicating that the software system for the Microblaze processor will be stored in ps7_ddr_1. Also, as the 'Vector Base Address' for Microblaze is set to the base address of ps7_ddr_1 during hardware development in Vivado, the program will start execution from the same memory sector upon wakeup.

• Similarly, in the application component ''hello_cortexa9" linker script, we can see that the linker sections of the application component are associated with the memory region with base address 0x0010_0000 and of size 0x1ff00000 which is 511 MB. The initial addresses are reserved for loading boot artifacts.

• This completes the software development for the design.

Running Software Applications on both Processors Simultaneously

Step 1: Setup the XSDB console and Serial Monitor

• Connect the Zedboard via UART and JTAG to the workstation and supply power to it.
• Open 'Serial Monitor' and 'XSDB Console' in Vitis Unified IDE.

Step 2: Program the Zedboard

• We wrote an xsdb script file, which will program the Zedboard.
• It will first open the target.
• Then, program the PL side with bitstream.
• Download FSBL to ARM Cortex A9 #0
• Download the RISC-V bootloop.elf in PS DDR memory. The bootloop file is required by the Microblaze so that it has some valid instructions to execute once it comes out of reset.
• Then we bring the Microblaze out of sleep mode by first configuring the Zynq7 EMIO GPIO to output and then writing Output as 1.
• Download Microblaze and ARM Cortex-A9 applications to their associated DDR memory regions.

# Open the target
connect
 
# Program the PL side  
fpga -no-rev -f D:/Vitis/Zedblaze/platform/hw/sdt/design_1_wrapper.bit
 
# Download FSBL to ARM Cortex A9 #0   
targets -set -nocase -filter {name =~ "APU"}
source D:/Vitis/Zedblaze/platform/hw/sdt/ps7_init.tcl;ps7_post_config
targets -set -filter {name =~ "ARM Cortex-A9 MPCore #0"}
dow D:/Vitis/Zedblaze/platform/zynq_fsbl/build/fsbl.elf
con
after 500

# Download the RISC-V bootloop.elf
dow D:/Vivado/Zedblaze/Zedblaze.gen/sources_1/bd/design_1/ip/design_1_microblaze_riscv_0_2/data/riscv_bootloop.elf
   
# Wake up Microblaze
targets -set -nocase -filter {name =~ "APU"}
mwr -force 0xE000A284 0x00000001
mwr -force 0xE000A048 0x00000001

# Download Microblaze Application
targets -set -nocase -filter {name =~ "RISC-V"}
targets -set -filter {name =~ "Hart #0"}
dow D:/Vitis/Zedblaze/hello_blaze/build/hello_blaze.elf
con

# Download ARM Cortex-A9 Application
targets -set -filter {name =~ "ARM Cortex-A9 MPCore #0"}
dow D:/Vitis/Zedblaze/hello_cortexa9/build/hello_cortexa9.elf
con         

Step 3: Final Output

• Here, we have arranged the XSDB console in the lower left corner of the screen and the serial monitor in the lower right corner of the screen.
• Run the XSDB script file given in the last step by executing the 'source' command in the XSDB console.

source D:/Vitis/Zedblaze/xsdb_script.txt        

References

1. Xilinx's Zynq 7000 Technical Reference Manual (UG 585)
2. Xilinx's Microblaze V User GuideXilinx's Microblaze V User Guide (UG 1629)
3. Xilinx's Vivado Design Suite User Guide (UG 895)