idea for exception during ARM's development PART II

Cache behavior in ARM has variable description for detail.

Base on the idea for ARM8, it look a lot of description for Physical Memory, Virtual memory and in different mode would case different exceptions.

 the PAGE has three type 4KB,16KB and 64KB. The virtual address has different translate process to make it as physical address. When combine with Cache behavior, the analysis during the exception debug cycle time would be more complex.

 Each command in different type would have some kinds of limitation when we try to use it. Different command set in each mode will help to isolate the work environment to make sure the system in a stable status.

Cache setting in No Cache, Write through and Write back cache enable/disable and some kind of different mode. When system keep in multitasking status, some kind of cache behavior might cause some exceptions by the cache behavior during the instruction or data access process.  In ARM specifications, these kinds of behavior take a lot of pages. In other world, it will be a good start when exception reproduced on the platform. EL0, EL1, EL2 and EL3 related registers will help to understand the platform status. 

   These information will help the developer to analysis the exception during developing cycle time.