IC packaging knowledge: What is wafer-level packaging technology?

Traditionally, the electrical connection between the IC chip and the outside is achieved by using metal leads to bond the I/O on the chip to the package carrier and through the package pins. With the reduction of the characteristic size of IC chips and the expansion of the integration scale, the spacing of I/O continues to decrease and the number continues to increase. When the I/O spacing is reduced to less than 70 um, the lead bonding technology is no longer applicable, and new technical avenues must be sought. Wafer-level packaging technology uses thin film redistribution to process, so that I/O can be distributed on the entire surface of the IC chip rather than just limited to the surrounding area of the narrow IC chip, thereby solving the electrical connection problem of high-density, fine-pitch I/O chips.

Among the many new packaging technologies, wafer-level packaging technology is the most innovative and attracted the most attention from the world. It is a sign of a revolutionary breakthrough in packaging technology. Wafer-level packaging technology takes wafers as the processing object, encapsulates, ages, and tests many chips on the wafers at the same time, and finally cuts them into a single device. It reduces the package size to the size of an IC chip, and the production cost is greatly reduced. The advantages of wafer-level packaging technology have attracted great attention since its emergence and quickly gained huge development and wide application.In portable products such as mobile phones, EPROM, IPD (integrated passive devices), analog chips and other devices in epistar-level packaging have been widely used.The types of devices using wafer-level packaging are constantly increasing, and wafer-level packaging technology is a new technology that is developing rapidly.

In order to improve the applicability of wafer-level packaging and expand its application scope, people are researching and developing various new technologies while solving problems in the process of industrialization, and conducting research on the current situation, application and development of wafer-level packaging technology.

Wafer-level packaging

The initial budding of WLP was driven by the manufacture of low-speed I/O (low-I/O) and low-speed transistor components for mobile phones, such as passive on-chip sensors and power transmission ICs. At present, WLP is in the development stage, driven by Bluetooth, GPS (global positioning system) components and sound cards and other applications, demand is gradually increasing. When it reaches the production stage of 3G mobile phones, it is expected that a variety of new mobile phone content applications will become another growth driver for WLP, including TV tuners, FM transmitters, and stack memory. As memory device manufacturers begin to gradually implement WLP, it will lead to model changes in the entire industry.

At present, wafer-level packaging technology has been widely used in flash memory, EEPROM, high-speed DRAM, SRAM, LCD drivers, radio frequency devices, logic devices, power/battery management devices and analog devices (voltage regulators, temperature sensors, controllers, operational amps, power amps) and other fields.Wafer-level packaging mainly adopts two basic technologies, thin film redistribution technology and bump formation.The former is used to convert the welding area distributed along the periphery of the chip into a bump welding area distributed in the form of a planar array on the surface of the chip. The latter is used to make bumps on the bump welding area to form an array of solder balls.

Film redistribution WL-CSP

Membrane redistribution WL-CSP is the most commonly used process today. Because of its low cost, it is very suitable for the requirements of high-volume, portable product board-level application reliability standards.Like other WLPS, thin film redistribution WL-CSP wafers are still made using conventional wafer processes.Before the wafer is sent to the WLP supplier, the wafer must be tested in order to classify the circuit and draw a wafer diagram of the qualified circuit. Before the wafer is redistributed, the layout of the device must be evaluated to confirm whether the wafer is suitable for solder ball redistribution.

A typical redistribution process, the resulting solder bumps are arranged in a plane array. In this process, BCB is used as the redistributed dielectric layer and Cu is used as the redistributed connection metal. The bottom metal layer (UBM) of the bump is deposited by sputtering method, and the solder paste is deposited by screen printing method and reflow. Among them, the bottom metal layer process is very critical to reduce intermetallic reactions and improve interconnection reliability.

The redistribution process is to rearrange the I/O pads on the surface of the device. In this example, two dielectric layers are used on the surface of the device, and a redistributed metallization layer sandwiched in the middle is used to change the distribution of I/O. After this process, the solder ball bumps are electroplated, so the chip becomes a WLP product.

The disadvantage of redistributing the lead bonding pad design into a solder ball array pad is that the WLP products produced cannot be the best in terms of device design, structure, or manufacturing cost. However, once it is proved to be technically feasible, then this circuit can be redesigned, so the additional redistribution can be eliminated. This situation has become a consensus. To this end, a biphasic determination procedure is specially defined. The next-generation change may be the integration of a redistribution layer in the last metal layer of the chip, or a new design of the shortest signal line to improve performance.

The redesign may require the addition of new software tools. Since the redesign can eliminate the additional redistribution process and related processes, the structure of the redesigned signal, power supply, and ground wire is very low. The polymer is used for flattening silicon wafers, providing the necessary protection for the chip, and as a standard surface coating. For film redistribution WLP, the single-layer polymer WLP method is a cost-effective design.

Production of wafer-level micro-bumps

Lead bonding has been considered a universal and reliable interconnection technology since its birth 50 years ago.However, with the rapid development of mobile communications, Internet e-commerce wireless access systems, Bluetooth systems and umbrella positioning system (GPS) technology, mobile phones have become the strongest and fastest growth driver of high-density memory. It is replacing the PC as the technology driver of high-density memory. The demand for lower cost, smaller form factor, higher-speed device performance, longer battery life, better heat dissipation, "green" technology and higher device reliability have led designers to set their sights on flip chip bump interconnection technology to replace traditional lead bonding technology.

The key technical driving force for the development of lead-tin bump technology comes from continuous device size tightening. Under the 130nm technical standard, about 30% of logic chips require bump technology. However, under the 90 nm technical standard, this data jumped to 60%. When it was developed to mass production of 65 nm devices, the demand for gold bump technology climbed to more than 80%.

WLP is based on BGA technology and is an improved and improved CSP. Some people also refer to WLP as wafer-level chip-size packaging (WLP-CSP). It not only fully embodies the technical advantages of BGA and CSP, but also is a sign of a revolutionary breakthrough in packaging technology. Wafer-level packaging technology adopts mass production process manufacturing technology, which can reduce the package size to the size of an IC chip, greatly reduce production costs, and integrate packaging with chip manufacturing, which will completely change the situation of separation between the chip manufacturing industry and the chip packaging industry. It is precisely because wafer-level packaging technology is of such importance that it has received great attention as soon as it appeared and quickly gained huge development and wide application.

Metallization layer under bumps (UBM)

In the flip chip interconnection method, the UBM layer is the key interface layer between the metal pad and the gold bump or solder bump on the IC. This layer is one of the key factors in flip chip packaging technology, and provides high-reliability electrical and mechanical connections for both the circuit of the chip and the solder bumps. The UBM layer between the bump and the I/O pad needs to have good enough adhesion to the metal pad and the wafer passivation layer; protect the metal pad in subsequent process steps; maintain low contact resistance between the metal pad and the bump; can be used as an effective diffusion barrier layer between the metal pad and the bump; and can be used as a seed layer deposited by solder bumps or gold bumps.

The UBM layer is usually achieved by depositing multiple layers of metal on the entire wafer surface. Techniques used to deposit UBM layers include evaporation, electroless plating, and sputtering deposition. In advanced packaging, wafer bump production is very critical from both a cost and a technical point of view. In the production of wafer bumps, metal deposition accounts for more than 50% of the total cost. The most common metal deposition steps in wafer bump production are the deposition of the metallized layer (UBM) under the bump and the deposition of the bump itself, which are generally achieved by electroplating process.

Electroplating technology can achieve very narrow bump pitch and maintain high yield. Moreover, the application range of this technology is also very wide, and bumps of different sizes, pitch and geometric shapes can be made. Electroplating technology has been more and more widely used in wafer bump production, becoming the most practical solution.

First, the production of the UBM layer is completed on the wafer.Then thick glue is deposited and exposed to form a template for electroplating solder. After electroplating, the photoresist is removed and the exposed UBM layer is etched. The last part of the process is reflow to form solder balls. The detailed process steps for electroplating to make micro-bumps are：

(1) Evaporate/sputter the metal layer of the seed conductive layer on the wafer；

(2) Rotate and apply a layer of photoresist on the wafer；

(3) Lithographic electrode window array pattern；

(4) Electroplating metal micro-inserts through small holes in the photoresist；

(5) Remove the photoresist；

(6) Etching the exposed seed crystal conductive layer.

(7) Coating a thick layer of photoresist on the metal insert；

(8) Set of engraved Au bumps；

(9) Etch off part of the thick glue, so that the protruding part of the metal insert can appear；

(10) Electroplated Au bumps；

(11) A thin layer of Au or Cu is deposited on top of the insert.

Coplanarity refers to the high degree of consistency of all bumps in the wafer, which has strict requirements in the flip chip bonding process. In flip chip bonding, the height change of the bumps will lead to uneven distribution of force, chip fragmentation, and electrical open circuit. The typical requirement for bump coplanarity is that the height difference of the bumps in the entire chip cannot be greater than 5μm.

Thick film lithography

Wafer-level process technologies, such as micro-pitch wafer bumps, lead pad redistribution, and integrated passive components, provide convenient solutions for many applications. At present, many IC and MEMS devices have applied these technologies. Using these technologies, device packaging and testing can be realized at the wafer level, and then subsequent cutting processes can be carried out. Usually advanced packaging technology involves a thick film process of 5 to 100 μm, such as thick glue spin coating, uniform exposure of thick glue with large ups and downs on the surface, and obtaining very steep thick glue side walls.The equal-magnification full-field exposure system is an equipment solution that can meet this demand. Its high output and low self-alignment cost make it the most competitive system for projection stepper machines in the field of thick film lithography.

Wafer-level packaging processes include metallization, lithography, dielectric deposition and thick film photoresist spin coating, solder deposition and reflow soldering. The graphical process usually involves using several layers of metal to make a metal layer under the bump (UBM) for the bump foundation. The conductivity of the connection between the bump and the wafer should be very good, and the passivation layer and the metal layer under the bump need to have good adhesion. The standard process flow of photoresist graphics includes cleaning, gluing, pre-baking, exposure, post-baking, development and film strengthening.Each step of the process needs to define a set of parameters, which have an impact on future processes. After the photoresist is graphically completed, solder or gold is filled into the hole by electroplating or evaporation method. The next step is to remove the photoresist and perform a reflow process in the oven to convert the columnar bumps into spherical bumps.

The thick photoresist coating will remain on the chip as a mask for manufacturing metal solder joint micro-molds. The redistribution coating can be modified into a bump pattern, or as a connection between the peripheral pads and the surface distribution pad array. These pad arrays are made of 5 to 100 μm thick polysilicon films with different electrical, chemical, mechanical, and thermal properties.Isolating traces in the redistribution area requires materials with high strength, high thermal stability, and low insulation coefficient. These materials have been successfully developed. One type of material is called polyimide (such as the PI series developed by DuPont), and the other insulating material is phenylpropylcyclobutene (Cyclotene; BCB) from Dow chemicals.PI and BCB are widely used in flip chip bump packaging and other packaging processes.

The use of thick-film photoresist pads, bumps, and micro-characteristic molds of the metal layer structure under the ball can meet the different needs in WLP. Although the commonly used metallized materials are tin-lead, gold and copper, several other materials can also be used to achieve it. Materials used in standardized applications require high-resolution graphic conversion and easy peeling properties. Many practical applications require a photoresist thickness of more than 100μm. In order to obtain such a thickness, manufacturers have developed suitable coating materials.

In order to meet these needs, manufacturers have developed corresponding materials and process equipment. Many materials can achieve "thin" photoresist coatings (i.e. 2-10 μm) on standard semiconductor process equipment. AZP4330 (Anzhi Electronic Materials Group) and Shipleys 955 (Rohm&Haas Company/Shipley Company) photoresists are used to achieve a thickness of 5~100μm photoresist film. The use of multi-layer coating process can achieve a photoresist coating with a film thickness of 25 μm, but this will increase production time and cost.AZ P4620 and SPR 220 single layers can achieve a thickness of 25 μm. For thicker coatings, the choice of material and thickness becomes smaller. When the required photoresist coating is obtained by single-layer deposition, there will be many benefits in terms of cost. Therefore, it is very necessary to develop a single layer of photoresist material with a thickness of 50 μm and above.For example, materials such as JSR THB-611P and AZPLP100XT of Anzhi Electronic Materials Group can achieve a single layer of photoresist coating with a thickness of 60 μm and above. The recent research work is mainly the use of AZ9260 to achieve a single-layer photoresist coating with a thickness of 65 μm and AZ50XT to achieve a single-layer photoresist with a thickness of 100 μm.

The thick film process has some special requirements for the system.The alignment system must be able to evenly identify the geometric pattern as the alignment mark over the entire glue thickness range and a specific height of the undulation of the wafer surface. Since the exposure source uses parallel light exposure without relying on the focus, it can be achieved by using a proximity lithography machine combined with the principle of shadow exposure. The requirements of the lithography process for the proximity mask alignment exposure machine include: high intensity, high uniformity, the wavelength of ultraviolet light coincides with the sensitive wavelength of the photoresist, submicron-level alignment accuracy, and maintaining an accurate, controllable and consistent gap between the mask and the wafer during the exposure process.

EVG's NanoAlign technology is designed with the highest alignment accuracy and resolution and the lowest cost of use as the design concept to highlight the advantages of full-field exposure technology. At present, all of his company's exposure machines have applied this technology. Its goals include active anomaly control and sub-100 nm dynamic alignment resolution. Its equipment includes special gluing equipment and contact/proximity exposure machines improved from standard models. The latest 200 mm EVG6200 Infinity and 300 mm EVG IQ Aligner exposure machines have good flexibility and a friendly customer interface, which can fully meet the industrial production of φ200 mm and φ300 mm wafers that require thick glue technology.

Wafer thinning

Chip thinning technology is essential in laminated chip packaging technology because it reduces the package placement height and enables the chips to be superimposed without increasing the total height of the laminated chip system. Smart cards and RFID are the thinnest single-chip application forms that reflect an important part of the requirements of thin wafers. Thinner chips can increase the reliability of thermal cycling and support thin products. However, the degree to which the chip is thin depends on the wafer diameter and the WLP process. The reason is that the thin wafer surface is prone to damage, causing microcracks, and causing epistar rupture in subsequent operations. Since wafer back grinding is the final step of the wafer processing process, the extent to which the wafer is to be thinned is limited by the WLP process. Therefore, wafer-level packaging is regarded as an extension of the wafer process, and the scope of application of the packaging process steps should be taken into account when designing the wafer process.

The poor matching of the coefficient of thermal expansion between silicon and the mounting substrate is an important reason for the fatigue failure of the encapsulated solder ball in the thermal cycle test and on-site use. In addition, this failure is also closely related to the strength of each component itself. The thinner the chip, the better the flexibility, and the fatigue resistance of the solder ball will definitely be improved. Therefore, thinning the wafer and thereby reducing the chip thickness is also one of the important measures to improve the reliability of solder bumps. It is undesirable to thin the epistar before wafer-level packaging processing, which can easily deform or even break the wafer. Wafer thinning after wafer-level packaging processing is completed is a better method, but it is more difficult to implement. Wafer and thinning technologies and equipment for wafer-level packaging manufacturing are under development.

Advantages of wafer-level packaging

Wafer-level packaging is based on BGA technology and is an improved and improved CSP, which fully reflects the technical advantages of BGA and CSP.It has many unique advantages：①The packaging processing efficiency is high, and it is manufactured in a mass production process in the form of wafers.；② It has the advantages of flip chip packaging, namely light, thin, short and small；③The cost of wafer-level packaging production facilities is low, and the manufacturing equipment of epistar can be fully utilized, and there is no need to invest in another packaging production line.；④The chip design and packaging design of wafer-level packaging can be considered uniformly and carried out at the same time, which will improve design efficiency and reduce design costs；⑤In the entire process of wafer-level packaging from chip manufacturing, packaging to product delivery to users, the intermediate links are greatly reduced and the cycle is shortened a lot, which will inevitably lead to a reduction in costs.；⑥The cost of wafer-level packaging is closely related to the number of chips on each epistar. The more chips on the wafer, the lower the cost of wafer-level packaging. Wafer-level packaging is the smallest low-cost package. Wafer-level packaging technology is a mass-produced chip packaging technology in the true sense.

The advantage of WLP is that it is a chip-scale packaging (CSP) technology suitable for smaller integrated circuits. Due to the use of parallel packaging and electronic testing technology at the wafer level, it increases production while significantly reducing chip area. Due to the use of parallel operations for chip connection at the wafer level, the cost of each I/O can be greatly reduced.In addition, the adoption of simplified wafer-level testing procedures will further reduce costs.Wafer-level packaging can be used to package and test chips at the wafer level.

The development trend of wafer-level packaging technology

Wafer-level packaging technology should strive to reduce costs, continuously improve reliability, and expand its application in large-scale ICS. In terms of solder ball technology, Pb-free solder ball technology and high Pb solder ball technology will be developed. With the continuous expansion of IC wafer size and the progress of process technology, IC manufacturers will research and develop a new generation of wafer-level packaging technology. This generation of technology can not only meet the needs of φ300 mm epistar, but also adapt to the recent emergence of copper wiring technology and low dielectric constant interlayer dielectric technology requirements. In addition, it is also required to improve the ability of wafer-level packaging to handle current and withstand temperature. WLBI (wafer-level testing and aging) technology is also an important topic that needs to be studied.WLBI technology is to directly perform electrical testing and aging on IC wafers, which is of great significance for wafer-level packaging to simplify the process flow and reduce production costs.

Conclusion: Wafer-level packaging technology is a low-cost mass-produced chip packaging technology. The wafer-level package is the same size as the chip and is the smallest miniature surface mount device. Due to a series of advantages of wafer-level packaging, wafer-level packaging technology is developing vigorously driven by the demand for miniaturization and low cost of modern electronic devices. Currently, wafer-level packaging technology is usually suitable for small-size chips with low I/O counts. The industry also needs to develop new technologies, reduce production costs, and develop wafer-level packaging for large-size chips and wafer-level packaging for fine-pitch solder ball arrays.

When choosing the packaging type of modern electronic devices, it is necessary to meet the design requirements and have the lowest cost. The existing level of wafer-level packaging is only one type of packaging to choose from. There is still a lot of work to be done to make wafer-level packaging technology the mainstream manufacturing technology for large-scale and wide-ranging products in the future. The design of combining semiconductor chips with WLP packages will undoubtedly bring benefits to the layout of WLP devices and improve device performance.In WLP, since the packaging steps of all devices on the wafer are carried out at the same time, batch processing can reduce packaging costs.