IC MASK DESIGN Q4 2023
IC Mask Design Q4 Newsletter
- NEWS
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IC Mask Design Technical Lead, Gaurav Masiwal?Presents at?CadenceLive 2023, Europe, Munich.
Congratulation to IC Mask Design Technical Lead, Gaurav Masiwal, who presented on "Real-time Parasitic Estimations using Width Spacing Patterns" at CadenceLive 2023 in Munich October 11th. A major challenge in the field of layout design lies in the post-layout parasitic extraction process, which often introduces delays and the potential for significant modifications in the layout. This paper introduces a novel approach to address this challenge, providing real-time parasitic estimations using Width Spacing Patterns (WSPs).? FIND OUT?MORE > ?
IC Mask Design's Technical Lead, Gaurav Masiwal to Host Webinar
IC Mask Design Technical Lead, Gaurav Masiwal, hosts a webinar on "Real-time Parasitic Estimations using Width Spacing Patterns" on Oct 24th,? 4pm GMT. REGISTER HERE?> ?
- ARTICLES
Recording of Webinar " FinFET UltraPcell Methodology"
In this webinar recording IC Mask Design's Technical Lead Jorge Araiza looks at the challenges of one of the main tasks a layout engineer has i.e., making a floorplan: WATCH VIDEO>
Layout Design Cycle Times and FinFET nodes;
IC Mask Design CTO Cíarán Whyte answers the common question does the Layout Design process take longer on FinFET nodes? WATCH VIDEO >
- TRAINING COURSES
IC Mask Designs Training Courses For 2023
?? FinFET – Nov 20th to 23rd. ?
All public courses are delivered on-line, if interested in registering for training courses please contact James Telfer at [email protected].