Hybrid Bonding is Picking Up Strongly

Intro

"Hybrid bonding is picking up strongly!" - these are the words of BESI CEO Richard Blickman in the Q3 results presentation on Nov-26. Almost like following an unwritten obligation every participant in the Q&A session had at least one question regarding the topic hybrid bonding. Since the announcement of the collaboration between AMAT & BESI on joint technology development for hybrid bonding in October last year and publishing an installed base forecast for hybrid bonders by BESI [1] the buzz-word "hybrid bonding" seems to drive a couple of analysts crazy in order to get substantial understanding of the technological and financial impacts.

A new business segment popping suddenly up (like the cat jumping out of the bag) with a cumulative estimate of 1-2 billion Euros (and I don't see indications why this estimate should not be trustable) is in the backend world extraordinary. Backend companies like BESI are usually faced with the challenge to perform well in a world of moderate growth while permanent considerable R&D efforts are just necessary to keep position with the main competitors. Just look at the OSATs, the broad technology spectrum they have to offer, the tremendous R&D efforts they have to spend, and then study the margins they are able to make! A "sudden" business opportunity like hybrid bonding may act like a booster for a well positioned backend company, in BESI's case it is expected that hybrid bonding boosts the company through the 1 billion revenue boundary.

At Besi I was most of my time in charge of developing emerging business segments: first flip-chip, then fan-out, finally thermo-compression bonding. For flip-chip it took 10 years to develop the business to a considerable size with a plurality of customers, and despite that Besi was the market leader, this size was smaller than the hybrid bonding segment is projected to be in the first two years of its lifetime. One significant difference to flip-chip, fan-out and thermo-compression is that hybrid bonders are not going to backend assembly floors, the destinations are frontend production floors where equipment price tags are 10-500 times higher than in backend, implying top healthy margins.

A top level foundry manager explained to me: "... this technology ..." (he regarded the total 3D SoC manufacturing process, for which hybrid bonding is only a small contributor) "... is neither an adoption of a backend process, nor is it a derivative of a frontend process - it's something completely new! It took us more than 10 years of development", which is a very clear statement that we are in midst of a disruptive technology transition. Currently we watch the cat just jumping out of the bag, and for me as a railroad fan it is now like watching the first electrified trains climbing up the Gotthard track, leaving decades of steam locomotives behind.

But wait a minute - when "they" (it is never one single company) worked more than 10 years on the process development, was it not predictable for backend companies that there is a cat in the bag? First of all: big guys like Intel, Samsung, TSMC, ... are not going to conferences and tell the world "hey, we have now a super trouper cool development in our pipeline, which will radically change the world in five years ...", why should they do so - to give their competitors and adrenalin kick?

Regarding disruptive developments they quietly meet up with a very selected group of suppliers and whisper to them sort of questions: "if we would need a machine with - assume - capability A, and maybe - assume - capability B, would you see a chance that you can make such a machine, and how would your approach look like?". No single word about details! No single word about the process the machine would run! No single word about timeline! - Unless you are in the final short list of one or two selected suppliers who are invited to quote an R&D tool based on a comprehensive spec.

Seeking for Mosaic Pieces

In the last 3 years of my Besi career (2016-2018) I had the luck of being assigned as a full time technology scout with an influencing role for management decisions for disruptive developments in order to serve upcoming markets. In this sense I collected mosaic pieces of a picture which one wishes to see in a crystal ball [2].

Once in 2016 I was escorted by an asian sales colleague to a cantina in the basement of a big foundry for a meeting with a project manager. This guy asked me whether I could imagine to build a pick&place machine with 50 nanometer placement accuracy.

After taking a deep, deep breath my first reaction was "why, the hell, is someone interested to place a chip with a precision 10x down the wave length of visible light?".??With a convincing voice I answered: "It might be a bit challenging, but I'm quite sure that such a machine can be built".

At this stage I have to add that when I started at Datacon in 1999 (the company which has been accquired 2004 by BESI and is now called BESI Austria) the grand-grand-grand-father of BESI's cash cow 2200 EVO, named DC95, was at a placement accuracy of 50 micrometers, and the topic of the discussion in the cantina was a 1000x stronger accuracy. When I was in charge of the flip-chip business the accuracy of the 8800 platform had to improve from 10 microns to 5 microns (a low hanging factor of 2x) in a timeframe of about 10 years. You can be sure that I did not have any clue how a machine can be built with an accuracy 40 times more accurate than what we have ever installed in a production floor so far.

A Shocking Demonstration

In my scout era I periodically spent some days at the IMEC in Belgium enjoying fruitful learnings from 3D-Guru Eric Beyne and his 3D team. One day in IMEC's clean room one of the most important mosaic piece jumped right away into my eyes. A 3D-team member demonstrated a direct bond (one of the principles underlying to hybrid bonding) on "our" (IMEC's) EVO machine. The guy used blank dies of a highly polished wafer (polished down to +/- 0.2 nanometers, the size of a silicon atom - get it!), which he cleaned in an improvised carrier in an ultrasonic DI-water bath. Then he semiautomatically operated the EVO to build-up chip-to-wafer 2-layer stacks.??To the big surprise of my colleague Alastair and me a direct (silicon-to-silicon) bond was performing right in front of our eyes, where the atomic Van-der-Waals forces attracted the two blank highly polished silicon surfaces ...

What? - That's it? What the hell "direct bonding"? And what the hell "Van-der-Waals forces"? How can you bond a die to a wafer without glue, without solder, without reflow, without heat application? No temperature involved? No compression force? That simple?

Front-end guys would not really be surprised of such scene. The effect was first mentioned by Desaguliers in 1734, and first witness of successful silicon direct bonding was reported in 1986. For me, as a backend guy, however, a new world! My colleague Alastair rolled his eyes, lifted his shoulders close to his ears and pressed his lips together to an evil grin, likely to say "simple and cool, isn't it?". But for me the demonstration was a pure shock. From that time I realized that all the efforts we have put into the development of thermo-compression bonders to support the take-off of DRAM-cubes was a waste of time, except that we gained very intensive relationship with high level memory guys, which was, by the way, of outstanding value.??

After this event, like a new baptized hybrid bonding evangelist, I could not do other than using "colorful words" for the established standard micro-bump assembly process (thermo-compression) [8].

Having realized the physical principles of direct bonding the IMEC is a predestinated location to learn much more about direct (fusion) bonding and hybrid bonding. In fact hybrid bonding in the sense of today's used buzz-word is an extension of direct dielectric bonding with direct copper bonding of copper pads embedded in the dielectric. Technically it is a much more challenging process than simple silicon direct bonding, but with similar underlying principles, especially the principle of being a cold bonding process without additional ingredients like glue or solder, which usually add tremendous complexity to a bonding interface.

If you visit the IMEC homepage today you find there: "Direct bonding of dies to silicon is also possible using?hybrid copper bonding. We are developing die-to-wafer hybrid bonding with pitches down to 3μm and high-tolerance pick-and-place accuracy, using what we learned in wafer-to-wafer hybrid bonding". And in a next paragraph you find: "For high-density wafer-to-wafer stacking, we are working towards hybrid bonding with ultra-low interconnect pitches, currently aiming at 500 nm pitch interconnects."

The pick&place guys use a rule-of-thumb: "given a certain interconnection pitch, the pick&place accuracy should be 10x lower!". Now take the 500nm pitch, lower it by a factor of 10 and here we are again: at 50nm placement accuracy - sure, at current times for wafer-to-wafer (W2W) processes, but chip-to-wafer (C2W) roadmaps always followed W2W!?

Who is interested in the outcomes of IMEC's 3D-Integration research program? The answer: those guys who are financing IMEC's research programs: Intel, TSMC, Samsung, Hynix, Micron, Qualcomm, ..., the most successful semiconductor players, companies in the top-10 list.??

When I was 1999 the first time in the Philippines an Amkor manager told me: "If you want to learn packaging then go to the sub-con" (packaging sub-contractor). 20 years later the paradigm changed: "If you want to learn 3D-integration then go to the IMEC".

Eric Beyne, director of IMEC's 3D system integration program tells us the actual challenges to be mastered: “Traditional CMOS technology scaling – resulting in monolithic CMOS single-chip systems-on-chip (SOCs) – will continue into the next decade through innovations in technology, materials and device architectures. CMOS scaling is increasingly being complemented by design-technology-co-optimization (DTCO) to improve the system’s power, performance, area and cost (PPAC). But with increasing cost and technology complexity, these approaches no longer deliver sufficient gains at the system level. This is especially true for data-intensive high-performance applications that are challenged by the so-called memory wall – the difficulty of accessing data quickly enough." What he says? Which wall? The memory wall !?

Completing the Mosaic

After having realized the seed I seeked out for relationships with the guys from Invensas/Xperi, the company who developed the ZiBond direct bonding and DBI hybrid bonding processes, one of the first direct/hybrid bonding processes being utilized (W2W) in mass volume devices - Sony's image sensors. I learnt a lot from the hybrid W2W bonding equipment gurus at EVG (isn't it funny that the market leaders of hybrid bonding equipment, BESI Austria and EVG are both located in my home country Austria). ?

A further essential mosaic piece was found in DARPA's CHIPS program, the "Common Heterogeneous Integration and IP Reuse Strategies", started in 2017. The program is nothing else than a booster for the rise of chiplets. Chiplets are functional, verified, re-usable, physical IP-block, embedded in an eco-system defining interface and assembly standards for rapid implementation of integrated systems with performance of monolithic systems-on-chip (SoC) [2].?

And what are now these "assembly standards for rapid system integration"? One early standard has been set with "Embedded Multi-Die Interconnection Bridge" (EMIB) by Intel for chip-to-substrate 2.5D integration, a second one has been implemented by TSMC with "System on Integrated Chips" (SoIC) for 2.5D and 3D silicon-to-silicon interconnection. And to complete the picture: SoIC uses hybrid bonding technology for the interconnection. Intel proposed a 3rd assembly standard FOVEROS for 3D chip-to-chip integration, where the variant FOVEROS-DIRECT is also utilizing hybrid bonding. Samsung's X-Cube platform still uses solder interface, so we wait for Samsung's hybrid bonded cat jumping out of the bag.

The picture of the crystal ball became clearer and clearer. At that time I was convinced that we can trust the picture built from the collected mosaic pieces. Finally we were able to formulate a proper advanced die attach roadmap for the new world [2].

And Besi started a couple of disruptive developments for next generation advanced packaging equipment with "Van Gogh" (sketched in [2], more details in [6,7]) as the killer approach for hybrid bonders in order to achieve hybrid bonding high speed at ultra high accuracy placement. The roadmap postulation in [2] claims 500nm down to 50 nm accuracy at 300mm wafer area with a throughput of 1000-5000 chips per hour for 3D-SOC hybrid bonding, Birgit Brandst?tter et. all talk in [7] about 200nm accuracy @ 2000 CPH development target, and Richard Blickman confirmed in the latest QnA session for investors that the current capability is already at 125nm accuracy @ 1500 CPH with a next step goal of 2000 CPH. The power of Van Gogh - really not bad, and a challenging benchmark for the competitors!

Today the landscape of chiplets (sometimes called dielets) and hybrid bonding is quite clear, but the challenge in 2017 was to assemble the mosaic pieces with the limited information access of a backend supplier, where most of the development in the R&D labs of the big guys was quite confidential. I remember lots of follow-up meetings with that company with the cantina in the basement (the meetings were this time with high level managers in the 3rd floor). Over almost one year they just told us the key capability specs which our machine would have to meet, and they asked questions over questions, how exactly our machine can make the impossible possible. But they never lost a word about what exactly will go on in the machine, especially what kind of interconnection process.

Which Product Drives BESI's Hybrid Bonder Ramp?

As everyone could hear from Richard Blickman, BESI received now double digit orders for hybrid bonders in Q3, and BESI is preparing for a ramp towards the capacity of about 150 hybrid bonders per year, or in other words, for a new business branch which is 100 to 300 million per year.?

But which product is driving such a steep ramp? Richard Blickman gave a small hint in his talk: When he came to comment on the important role of chiplets, he mentioned "... a nice example was the analyst update of ASML where you could see a chiplet, an AMD chiplet, where Besi is also involved". So let's look-up ASML's latest Technology Strategy presentation [3]. We find AMD-CEO Lisa Su showing proudly an R&D sample of a Ryzen 5900X processor, built with 3D chiplet technology with key labels "3x power reduction" and "4-25% speed improvement" - two rather bold statements! In smaller text we finally find "Direct copper-to-copper bond", the key ingredient of a hybrid bond.?

In Lisa Su's keynote from 02-Jun-2021 she explains in big detail that AMD closely partnered with TSMC in the past few years to utilize TSMC's 3D chiplet integration technology (SoIC) which has production start by the end of this year. AMD's first application is a 3D-integrated chiplet based L3 vertical cache extension for the Ryzen core complex chiplets (processor cores).

Remember: the memory wall! Eric Beyne mentioned it: the difficulty of accessing data quickly enough! So what - did we miss the section where Lisa Su talked about the memory wall in her keynote? - No, Lisa Su did not talk about the memory wall - she and her team jumped right away over the wall by utilization of TSMS's hybrid bonding based SoIC technology!

The benefits compared to 2D chiplet technology (introduced by AMD in??2019) are:

• ?200x interconnect density of 2D chiplets
• more than 15x interconnect density compared to other 3D stacking solutions
• 1/3 the energy per signal of micro bump 3D approaches?

Would you love that your notebook's battery lifetime increases by a factor of three? - Yes, really? Are you advocating that cloud server farms should consume three times less power in order to save our environment for our children? - Yes, really? Are you mad that your smart phone runs out of battery when you have frequent video calls, and would you love that the battery lifetime of your phone and smart watch increases by a factor of three? - Yes, really? - then you probably started by this moment to become a fan of hybrid bonding!

Let us look to the other side of the river. At the web page of TSMC [5] we see a big promotion of their SoIC technology for the fabrication of 3D integrated chiplet stacks. As benefits TSMC promotes:

• 10x speed
• 20x energy efficiency
• 190x bandwidth improvement

?a total benefit improvement of 10 x 20 x 190 = 38.000 (get it!)

This makes clear that 3D integrated chiplet technology is a disruptive technology, hybrid bonding is the underlying interconnect technology, and according to Richard Blickman, "BESI has a well developed market position in the hybrid bonding segment", a statement which cannot be doubted when we trust the double digit hybrid bonder orders of Q3.?

Epilog - Travel Tourists and "Holzk?pfe"

In my whole semiconductor career I never had the feeling that the competition was sleeping. When you had a clever idea - voila! - also a competitor came with a good approach! When you thought you had a good move - voila! - your main competitor had also a smart move! In this whole hybrid bonding development history, however, I had the feeling that the competitors of Besi were sleeping.?

Maybe this is a big mis-perception! Otherwise, one has to ask, what is the reason to leave Besi the game of developing this strong market position? Can you imagine a management acting in a slowly growing market, which is aware of a significant technology change with tremendous business impact, and decides to let such an opportunity go?

So what was the reason that Besi started the right developments so early, and the competitors did not? Was it a fatal mis-conclusion that 3D-SoC manufacturing is an exclusive game for W2W-suppliers like my Austrian friends at EVG? Or was it the simple reason that Besi management "downgraded" a successful business development VP to a simple travel tourist with the role of a technology scout, messing around on conference receptions, in the basement cantinas of foundries, in the clean rooms of the biggest memory makers and research institutes (they gave me the nick name "Cleanroom VP"), and on "Bill&Bill's conspiracy meetings of crystal ball gazers" (Bill Chen and Bill Bottoms are the fathers behind the Heterogeneous Integration Roadmap) in order to collect mosaic pieces like souvenirs? And was it the reason that the competition did not decide to have such kind of travel tourist? Who knows?

As a Besi shareholder I have to be greatful to Besi CEO Richard Blickman, who runs the company with excellent financial performance and made the final decision for the investment into disruptive developments for hybrid bonding business at the right time. As a technology guy, however, a much bigger respect goes to CTO and former boss Ruurd Boomsma who always looked seriously at my mosaic pieces and finally enabled his R&D team to get grip on the ground.

The biggest respect, however, goes to all those technology warriors in Radfeld (BESI Austria's location), who do neither care whether my share values increase or loose value, but have permanently only one single goal in front of their eyes: "be faster and better than the competition, and in no case (no case !!!) let the customer down!" (many of their names can be found in [7]). I know from personal experience how hard work it is for R&D guys to boost a fairly mature equipment through a steep ramp, while concurrently improving the maturity. This is the daily life of emerging business. We had it in flip chip, we had it in fan-out, we had it in thermo-compression, and also all our competitors in these sectors had it! Why should it now be different for hybrid bonding?

A previous Besi executive (who has also my deep respect) used also colorful language to call these technology warriors in Radfeld (including my own person) "Tiroler Holzk?pfe" (Tyrolean wooden heads). My deep congrats goes to those "Tiroler Holzk?pfe" for achieving what has been achieved so far and making the impossible possible, and I'm deeply convinced that they once again demonstrate to the world that the leading technology for the game changer in advanced packaging scene comes from my home country Tyrol. Finally I look forward to hear once about BESI's 50 nm bonder, a pick&place machine 1000x more accurate than the Datacon bonders I dealt with, when I started my semiconductor career by the end of last millenium.??

References

[1] BESI Investor Presentation, August 2021; https://www.besi.com/fileadmin/data/Investor_Relations/Investor_Presentations/Investor_Presentation_Aug_2021.pdf

[2] H. Pristauz, A. Mayr, S. Behler: Disruptive Developments for Advanced Die Attach to Tackle the Challenges of Heterogeneous Integration; ECTC 2018; https://ectc.net/files/68/Behler%20Besi%20paper.pdf

[3] Martin van den Brink: Technology Strategy; ASML Investor Day 29-Sep-2021, page 14; https://www.asml.com/en/investors/investor-days/2021

[4] Lisa Su: AMD at Computex 2021; https://www.youtube.com/watch?v=gqAYMx34euU

[5] The Whats, Whys, and Hows of TSMC-SoIC; https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/SoIC_inDepth.htm

[6] N. Bilewicz, A. Mayr, H. Pristauz, H. Selhofer, “Apparatus and?Method for Mounting Components on a Substrate,” US patent, US 2018/0317353, 2018. patent;https://patents.google.com/patent/US20210195816A1/en?oq=20210195816

[7] Birgit Brandst?tter et. all: High-speed ultra-accurate direct C2W bonding; ECTC 70th (2020); https://www.besi.com/fileadmin/data/Articles/High-speed_ultra-accurate_direct_C2W_bonding.pdf

[8] Francoise von Trapp: Hugo Pristauz Drops the F-bomb at 3D ASIP 2016; 3DInCites blog Dec. 20, 2016; https://www.3dincites.com/2016/12/hugo-pristauz-drops-the-f-bomb-at-3d-asip-2016-you-wont-believe-what-happens-next/