How Wafer Stress Measurement Can Enhance Semiconductor Yield

Introduction

From 2008 to 2018 the electronics market have grown to 250 billion dollars. These all electronic devices fully depends on the related IC or wafers. If we do not make good qualities wafer, then the semiconductor fabrication industry would have faced tremendous losses. Every year Intel, Samsung, Taiwan semiconductor, Qualcomm, Broadcom, SK Hynix, Micron Technology, Texas Instruments, Toshiba, NXP Semiconductors and many other companies all over the world are facing losses of almost 100 billion Dollars, only because of defected wafer. That’s why, defect inspection important.

Significance of stress measurement

Especially as film thicknesses and other feature dimensions become smaller, film stress plays an important role in the manufacturing process. Stress is accumulated during each of the hundreds of fabrication and processing steps involved in creating a thin film structure. Examples of known phenomena and processes that build up stresses in thin films include lattice mismatch, chemical reaction, doping by diffusion or implantation, and rapid deposition by evaporation or sputtering. Film stress buildup can lead to failure through many mechanisms, including stress-induced film cracking, buckling and delamination for brittle dielectric films, and through void nucleation and growth for more ductile metal films. Therefore, the accurate measurement and analysis of the film stress and stress distribution associated with each processing step. And modification of the processes is needed for establishing appropriate product quality control methodologies. Indirectly, electronic industry of the whole world is fully depend on “the film stress & wafer Bow measurement system”.

Measurement of film stress

When thin films are deposited at high temperature or annealed at high temperature, intrinsic stresses develop in the film due to mismatch of thermal expansion coefficients between the film and substrate material. The wafer will visibly bow or bend to a measurable degree based on the stress developed in the film.

Thin film stress is calculated by measuring the change in radius of curvature of a substrate caused by the deposition of a thin film on the substrate. The thin film must only be on one side of the sample (front), because if it is on both, it will balance the stress. This requires measurement of the original substrate radius of curvature followed by a second curvature measurement after the film of interest has been deposited on the front (single side) of the substrate. If the film is deposited on both sides of the substrate, it must be removed on the back.

Stress is generally measured by Stoney's Equation

Stoney’s Equation,

Where, E = Young’s Modulus, v = Poisson’s Ratio, D = Substrate thickness, t = Film Thickness, R = Radius curvature change

R is derived from following measurement during the scanning:

here, L = Beam path; δd/d0= the differential beam spacing caused by a bending of the film/substrate stack due to differences in film stress and thermal expansion coefficient. The high resolution of the differential beam spacing δdd0 ensures the high measurement sensitivity of about 6×10-5 GPa.μm stress-thickness product.

Prospects of Stress Measurement

The evaluation of “Stress Measurement” in silicon devices is extremely important in the development of next generation, high precision, highly integrated devices. Therefore, the accurate measurement and analysis of the film stress and stress distribution associated with each processing step, and modification of the processes as needed, is necessary for establishing appropriate product quality control methodologies.

• Stress and flatness measurements are an integral part of the process of reliability monitoring of deposited thin films during the chip making process.
• Some of these stress related problems may be exhibited as metal and dielectric film cracking, hillock formation, voiding, and film lifting. 

Thin film metrology is used to tightly control the thickness, refractive index and extinction coefficient of photoresist and other coatings. Wafer test metrology equipment is used to verify that the wafers haven't been damaged by previous processing steps up until testing; if too many dies on one wafer have failed, the entire wafer is scrapped to avoid the costs of further processing. These all steps are done by the “The film stress & wafer Bow measurement system”.

Stress Measurement Devices

Frontier Semiconductor (www.frontiersemi.com), offers a range of advanced metrology products for semiconductor applications, including Measurement Systems for Film Stress. Stress and wafer bow maps can be acquired over the entire wafer surface, providing process engineers means to characterize and develop new processes using different thin film materials.

The FSM 128 Series systems are room temperature, full-wafer 2D/3D stress mapping systems. 128 systems use FSM's patented non-contact, opti-lever, dual-laser auto-switching technology featuring a micro positioning detector to measure the laser beam deflection with high precision over a large dynamic range of small to large bow or stress. FSM's stress gauges have the ability to scan 1000 points per inch in seconds for high resolution, high precision stress mapping on blanked and patterned wafers. Here some of our products related to stress measurement

• Dedicated Film Stress mapping system with high resolution for high throughput process control for wafers up to 200mm diameter. Fully automated cassette to cassette, SECS/GEM Film Stress and Bow Measurement tool.
• Film Stress Measurement Range: 1 MPA to '1.4 GPA for a typical Si wafer (provided curvature or bow height charge is at least 1 micron)
• Repeatability: 1 % ( 1 sigma ) on a 20m curvature
• Accuracy: Better than 2.5%