How to Select a Clock inside the AURIX? GTM

The?Generic Timer Module (GTM) in the AURIX? provides peripherals to measure and generate complex timing signals. These include the Timer Input Module (TIM), and the Timer Output Modules ?(TOM/ATOM).

For the AURIX? TC3xx series of microprocessors, at the heart of the GTM block is a Clock and Time Base Module (CTBM). This is located inside GTM Cluster 0, which provides infra structure support for clocks to the rest of the GTM sub-modules. This CTBM module provides the clocks to allow the TIM to accurately measure input events and to capture time stamps on the signal edges. Similarly, the CTBM provides clocks to the TOM/ATOM sub modules for generating complex timing output waveforms.

With so many signal paths for the clocks it is sometimes difficult to know how best to organise them, especially at the start of a project.

This article provides an overview of the CTBM module and some guidance?on how to organise the clocks for a complex GTM based application.?

The CTBM comprises of four sub modules, the Clock Management Unit (CMU), the Time-Base Unit (TBU), the Digital Phase Locked Loop (DPLL) and the Mapping module (MAP). A summary of the four blocks is provided below.?

The CMU provides a series of clock signals, including external clocks to IO pins (EGU), user configurable divider clocks (CFGU), and fixed divider clocks (FXU). The CFGU clocks are used to clock the ATOMs and the TIMs, whilst the FXU clocks are used to clock the TOMs.

The Time Base Unit (TBU) is designed to provide a series of 24bit counters which can be captured by the various peripherals and used as timestamps. Consecutive timestamp capture allows for the measurement of signal periods. It is possible for the digital phase locked loop (DPLL) inside the CTBM to provide angle related data to some of the TBUs, which when captured provides an angle-stamp. Both angle stamps and time stamps can be used together to help synchronise complex sequences, such as engine injection and ignition events.

The mapping module allows signals processed by the input TIM modules to be routed through to the DPLL module. The TIM related output signals are generally the filtered outputs of the GTM-TIM input pins.

The CTBM module has its own DPLL, (not to be confused with the system clock DPLL). The DPLL pulses are routed to it from the mapping module. These are then multiplied up to provide a higher frequency output than the incoming signal. Typically, a multiplication of 100 is used. The higher rate ?DPLL output provides better resolution than the lower rate DPLL input. For example, 60 pulses per second from the GTM-TIM can be multiplied up to achieve 6000 pulses per second at the DPLL output. The DPLL can provide its output signals to both the CMU and the TBU sub modules.

When first devising a clock arrangement for the CTBM, the user must know the limitations of the TIM input and TOM/ATOM output signal frequencies, and the minimum resolution to which these?signals are used. The user can then work backwards to determine suitable clocks rates for the various sub modules and in turn the required frequencies from the CTBM.

So, for example a 25KHz PWM has a period of 40us. With a 4000 counts resolution, the timer tick to the input of the ATOM would be 40us/4000 = 10ns timer tick. As Cluster 0 which contains the CTBM module can operate at 200MHz (5ns timer tick), the user could choose a clock for the ATOM to be 5ns or 10ns timer tick. In the case of 5ns timer tick the ATOM would have twice the resolution at 8000 counts rather than 4000 counts. ATOMs are clock by configurable clocks (CFGU) ?and so one of the clocks can be configured accordingly to provide the correct divide ratio.

If the user was to choose a TOM module instead then the TOM would need to use one of the fixed clocks (FXU). As the clock dividers are fixed the choice of using a TOM over an ATOM would impact the clock tree more significantly.

The GTM-TIM input modules require three clocks. These are used for the input filter stages, the timer logic block and the timeout detect circuit. The choice of clock for the filter stage is restricted to a limited selection of configurable clocks, whilst the other two can use any of the eight available configurable clocks.

So, as can be seen the clock organisation gets very complicated very quickly, and so its prudent to develop a spreadsheet which can calculate all the required clocks starting from the GTM cluster 0 input clock frequency.?

An example set up is shown below. In this example the TIM is supplied with one CFGU clock (CMU_CLK0), shared with?the input filter and the timer control block. The TIM is configured to capture timestamps from TBU-TS0 and TS1 which capture time stamps and angle stamps respectively. TBU_TS0 is clocked from the CFGU (CMU_CLK0) whilst TBU_TS1 is clocked from the TIM filter output via the DPLL.

The CTBM-CMU provides clocks for the TIM input filters and the TIM signal processing.

The CTBM-TBU provides timestamp which and then subsequently captured by the GTM-TIM on input edge events, to provide rotational speed measurement. Finally, one TBU is configured to accept signals from the DPLL, which provides an angle stamp, which is also captured by the GTM-TIM.

During a service request generated by the TIM, the interrupt handler can capture all the ?dynamic data such as sensor level value, rotation speed, timestamp, and angle-stamp.

The GTM is one of the most complicated peripherals on the AURIX? device, but with careful consideration it is possible to devise a clocking strategy for the application. Having some known requirements for period and resolution for the TIM/TOM/ATOM sub modules will allow the software architect to create a clock spreadsheet which can then be translated into code by the software team.?

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