How will DRAM shrink?

At the SPIE Advanced Lithography Conference held in February 2021, Regina Pendulum of Applied Materials delivered a speech entitled "Module-Level Material Engineering for Continued DRAM Scaling". In the speech, Regina emphasized that the shrinking of DRAM is slowing down, and new solutions are needed to continue to increase the density, as shown in Figure 1.

Figure 1. DRAM node and bit density trends.

According to their introduction, the miniaturization of DRAM has ushered in many challenges:

Patterning-how to create increasingly dense patterns.

Capacitors-Evolve from a cylinder to a columnar structure, requiring a high aspect ratio to be patterned.

Resistor/Capacitance-The bit line and word line need to increase the resistance/capacitance to increase the access speed.

Peripheral (Peri) transistors-the evolution from polysilicon gates containing silicon oxide to high-k metal gates (HKMG).

Figure 2. DRAM expansion challenge.

This article will focus on patterning and capacitors.

Capacitor patterning has recently been completed by cross self-aligned double patterning (XSADP), but it is now being developed into even more complex cross self-aligned double patterning ((XSADP) but is now evolving to even more complex: XSAQP). As disclosed by Samsung, another option is spacer-assisted patterning, which can increase the hole density on the mask by a factor of 3, but requires etching to make the hole sizes equal. Recently, EUV has begun to be applied to the production of DRAM.

The author pointed out that Samsung is using EUV for the first-level province of 1z DRAM, and it is expected to use EUV for multi-layer 1α DRAM now. SK Hynix is also expected to launch its 1α DRAM using EUV lithography machine this year.

However, the implementation of EUV for DRAM faces the following challenges:

Local Critical Dimension Uniformity (LCDU), this change will change the electrical performance and etching aspect ratio.

Hole size-EUV is sensitive to hole size and has a narrow processing window.

Thin resist-EUV resist is very thin and needs to be hardened.

The use of thin deposits can harden the resist, and the use of thick deposits can reduce the critical dimensions (CD). The spatial selective deposition on the top of the pattern can improve Line Edge Roughness (LER)/Line Width Roughness (LWR), which is a significant disadvantage in EUV pattern formation. See Figure 3.

Figure 3. Improvements using deposited photoresist.

For active area scaling, EUV has a defect problem on large CDs. Instead, you can etch small holes and then use precise lateral etching to open the feature in one direction, thereby reducing the tip-to-tip distance. This technology eliminates the trade-off between CD and yield, and enables ovals to have a larger contact pad area, as shown in Figure 4.

Figure 4. Precision lateral etching for active patterns.

One of the main problems of EUV is the narrow process window, which can accept acceptable random defects. Directional etching provides an additional knobs for the process design. If the middle of the process window is opened and bridged, you can move to the side of the window with the bridge, and then use the directional etching to remove the bridge, see Figure 5.

Figure 5. Directional etching to eliminate random defects.

Today's capacitor pitch limit is greater than 40nm, which is also the EUV limit for current capacitor patterning. In the future, smaller pitches will be required, and process variability needs to be increased by more than 30% to achieve scaling, see Figure 6.

Figure 6. Capacitor scaling is limited by changes.

Reducing the thickness of the hard mask and improving the uniformity of the etching are all necessary to achieve this goal.

Nowadays, amorphous silicon (a-Si) is used as a hard mask. In the future, doped silicon can provide better selectivity, so that thinner hard masks can be realized, but it will produce by-products that are difficult to remove. See Figure 7.

Figure 7. Improved hard mask for capacitor scaling.

The problem with doped silicon for hard masks is that it requires special etching, and the next generation process uses high temperature etching. The photoresist is used to pattern the oxide hard mask; then the doped polysilicon hard mask is patterned using the oxide hard mask in the high temperature etcher, and finally the doped polysilicon hard mask is used Etch the capacitor. The stepwise pulsed etching switching between etching and deposition steps allows for radical chemical use of high-speed etching of capacitors, see Figure 8.

Figure 8. Improved performance and productivity.

It is expected that the above-mentioned process innovations can achieve continuous scaling of the current DRAM architecture.

But from the speech we saw that in 3 to 5 years, we will need a new DRAM architecture. An interesting option involved is 3D, which changes the capacitor from a vertical structure to a stacked horizontal structure.