How is the chip designed?

How is the chip designed?

Everyone is from the electronics industry, and we know a lot about chips and various packages, but do you know how a chip is designed? Do you know how the designed chip is produced? After reading this article, you will have a general understanding.

Complicated and cumbersome chip design process

The process of chip manufacturing is like building a house with Lego. First, the wafer is used as the foundation, and after the chip manufacturing process is stacked layer by layer, the necessary IC chips can be produced (these will be introduced later). However, it is useless to have strong manufacturing capabilities without blueprints, so the role of the architect is very important. But who exactly is the architect in IC design? The next part of this article is to introduce IC design.

In the IC production process, ICs are mostly planned and designed by professional IC design companies, such as MediaTek, Qualcomm, Intel and other well-known manufacturers, all design their own IC chips, providing chips with different specifications and performance for downstream manufacturers to choose. Because ICs are designed by each factory, IC design relies heavily on the skills of engineers, and the quality of engineers affects the value of an enterprise. However, what steps do engineers take when designing an IC chip? The design process can be simply divided into the following.

Design the first step, set goals

In IC design, the most important step is specification development. This step is like deciding how many rooms, bathrooms, and what building codes need to be followed before designing a building. After all functions are determined, the design is carried out, so that there is no need to spend extra time on subsequent modifications. IC design also needs to go through similar steps to ensure that the designed chip will not have any errors.

The first step in specification formulation is to determine the purpose and performance of the IC, and to set the general direction. The next step is to see which protocols must be complied with. Chips such as wireless network cards need to comply with IEEE 802.11 and other specifications. Otherwise, the chip will not be compatible with products on the market, making it impossible to connect with other devices. Finally, the implementation method of this IC is established, different functions are assigned to different units, and the method of connection between different units is established, so as to complete the formulation of specifications.

After designing the specifications, the next step is to design the details of the chip. This step is like taking a preliminary note of the building's plan and drawing the overall outline to facilitate subsequent drawing. In an IC chip, a hardware description language (HDL) is used to describe the circuit. Commonly used HDLs are Verilog, VHDL, etc. The functions of an IC can be easily expressed through code. The next step is to check the correctness of the function of the program and continue to modify it until it meets the desired function.

With a computer, things are easier

After having a complete plan, the next step is to draw a flat design blueprint. In IC design, the step of logic synthesis is to put the correct HDL code into the electronic design automation tool (EDA tool), and let the computer convert the HDL code into a logic circuit to generate the following circuit diagram. After that, iteratively determine whether the logic gate design meets the specifications and modify it until the function is correct.

The result after control unit synthesis.

Finally, put the synthesized code into another set of EDA tool for circuit layout and routing (Place And Route). After continuous testing, the following circuit diagram will be formed. In the picture, you can see different colors such as blue, red, green, and yellow, and each different color represents a mask. As for how to use the mask?

Layers of masks, stacking a chip

First of all, it is already known that an IC will produce multiple masks. These masks have upper and lower layers, and each layer has its own task. The figure below is a simple example of a photomask, taking CMOS, the most basic component in an integrated circuit, as an example. The full name of CMOS is Complementary metal-oxide-semiconductor, which is to combine NMOS and PMOS combined to form a CMOS. As for what is a metal oxide semiconductor (MOS)? This kind of component widely used in the chip is more difficult to explain, and it is also difficult for ordinary readers to understand, so I won't go into detail here.

At this point, you should have a preliminary understanding of IC design. Overall, it is clear that IC design is a very complex profession. Thanks to the maturity of computer-aided software, IC design can be accelerated. IC design factories rely heavily on the wisdom of engineers. Each step described here has its own specialized knowledge and can be independently divided into multiple professional courses. For example, writing a hardware description language is not simple, but only requires familiarity with programming languages. , you also need to understand how logic circuits work, how to convert the required algorithms into programs, and how synthesis software converts programs into logic gates.

The main semiconductor design companies are Intel, Qualcomm, Broadcom, NVIDIA, Meiman, Xilinx, Altera, MediaTek, HiSilicon, Spreadtrum, ZTE Microelectronics, Huada, Datang, Zhixin, Duntai, Silan, Zhongxing , Geco, etc.

What is a wafer?

In the semiconductor news, fabs are always mentioned in terms of size, such as 8-inch or 12-inch fabs. However, what are the so-called wafers? What part does 8 inches refer to? How difficult is it to produce large-sized wafers? The following is a step-by-step introduction to the most important foundation of semiconductors - what is a "wafer".

Wafers are the basis for the manufacture of various computer chips. We can compare chip manufacturing to building a house with Lego blocks, and by stacking layer by layer, we can complete our desired shape (that is, all kinds of chips). However, if there is no good foundation, the built house will be crooked and unsatisfactory. In order to make a perfect house, a stable base plate is required. For chip manufacturing, this substrate is the wafer described next.

First of all, recall that when I was a child with Lego blocks, there would be a small round protrusion on the surface of the blocks. With this structure, we can stably stack the two blocks together without using glue. . Chip manufacturing, in a similar way, holds the subsequently added atoms together with the substrate. Therefore, we need to find substrates with neat surfaces to meet the conditions required for subsequent fabrication.

In solid materials, there is a special crystal structure - monocrystalline (Monocrystalline). It has the property of atoms closely arranged one after the other, which can form a flat atomic surface. Therefore, using a single crystal to make a wafer can meet the above requirements. However, how to produce such a material, there are mainly two steps, namely purification and crystal pulling, after which such a material can be completed.

How to make a single crystal wafer

Purification is divided into two stages. The first step is metallurgical purification. This process is mainly to add carbon to convert silicon oxide into silicon with a purity of more than 98% by means of redox. Most of the refining of metals, such as iron or copper, is done in this way to obtain metals of sufficient purity. However, 98% is still not enough for chip manufacturing and still needs to be further improved. Therefore, the Siemens process will be used for further purification, so that the high-purity polysilicon required for the semiconductor process will be obtained.

Silicon pillar fabrication process (Source: Wikipedia)

Next, is the crystal pulling step. First, the previously obtained high-purity polysilicon is melted to form liquid silicon. After that, the single crystal silicon seed (seed) is brought into contact with the liquid surface, and is slowly pulled up while rotating. As for why single-crystal silicon seeds are needed, it is because silicon atoms are arranged in the same way as people line up, and they will need to be in the first place so that later people can arrange them correctly. Finally, after the silicon atoms leaving the liquid surface solidify, the neatly arranged single crystal silicon pillars are completed.

Monocrystalline silicon pillars (Souse: Wikipedia)

However, what do 8 inches and 12 inches represent? He's referring to the diameter of the crystal pillars we produce, the parts that look like pencil barrels, after the surface has been treated and sliced into thin discs. How difficult is it to make large wafers? As mentioned earlier, the production process of the crystal column is like making marshmallows, and it is formed while rotating. Anyone who has made marshmallows should know that it is quite difficult to make large and solid marshmallows, and the process of pulling crystals is the same. The speed of rotation and temperature control will affect the quality of the crystal column. Therefore, the larger the size, the higher the speed and temperature requirements for crystal pulling, so it is more difficult to make high-quality 12-inch wafers than 8-inch wafers.

However, a whole silicon pillar cannot be used as a substrate for chip manufacturing. In order to generate silicon wafers one by one, a diamond knife is used to cut the silicon pillars into wafers horizontally, and the wafers can be polished to form chips. Fabricate the required silicon wafers. After so many steps, the fabrication of the chip substrate is complete, and the next step is the step of stacking the house, which is chip fabrication. As for how to make chips?

Chips built on top of each other

After introducing what a silicon wafer is, at the same time, I also know that making an IC chip is like building a house with Lego blocks, creating the desired shape by stacking layer by layer. However, there are quite a few steps in building a house, as is IC manufacturing. What exactly are the steps involved in making an IC? This article will introduce the process of IC chip manufacturing.

Before we start, we must first understand what an IC chip is. IC, the full name of the integrated circuit (Integrated Circuit), from its name shows that it is a combination of designed circuits in a stacked manner. By this method, we can reduce the area required to connect the circuit.

First of all, here the red part can be compared to the lobby on the first floor in a tall building. The lobby on the first floor is the door of a house, and the entrance and exit are from here, and there are usually more functions under the control of traffic. Therefore, compared with other floors, the construction is more complicated and requires more steps. In the IC circuit, this hall is the logic gate layer, which is the most important part of the entire IC. By combining various logic gates together, a fully functional IC chip is completed.

The yellow part is like a normal floor. Compared with the first floor, there will not be too complicated structure, and each floor will not have too many changes during construction. The purpose of this layer is to connect the logic gates of the red part together. The reason why so many layers are needed is because there are too many lines to connect together, and when a single layer cannot accommodate all the lines, it is necessary to stack several layers to achieve this goal. In this, the lines of different layers will be connected up and down to meet the wiring requirements.

Layer-by-layer construction, layer-by-layer structure

Now that you know the structure of an IC, let's talk about how to make it. Just imagine, if we want to make detailed drawings with paint spray cans, we need to cut out the cover plate of the pattern and cover it on the paper. Then spray the paint evenly on the paper, and remove the shutter after the paint dries. After repeating this step continuously, neat and complex graphics can be completed. Manufacturing ICs is done in a similar way, layer by layer by masking.

When making an IC, it can be easily divided into the above four steps. Although the actual manufacturing steps will be different and the materials used will be different, but generally they all use similar principles. This process is slightly different from paint painting. IC manufacturing is to paint first and then cover, while paint painting is to cover first and then paint. Each process will be described below.

Metal sputtering: evenly sprinkle the metal material to be used on the wafer to form a thin film.

Coating photoresist: first put the photoresist material on the wafer, pass through the photomask (the principle of the photomask will be explained next time), and hit the light beam on the unnecessary part to destroy the photoresist material structure. Next, the damaged material is washed away with chemicals.

Etching technology: The silicon wafer that is not protected by photoresist is etched by ion beam.

Photoresist removal: Use the photoresist removal solution to dissolve the remaining photoresist, thus completing a process.

In the end, many IC chips will be completed on a whole wafer. Next, as long as the completed square IC chips are cut out, they can be sent to the packaging factory for packaging. As for what is the packaging factory? We will explain it later.

Among them, the main foundries are GlobalFoundries, Samsung Electronics, Tower Jazz, Dongbu, Magna, IBM, Fujitsu, Intel, Hynix, TSMC, UMC, SMIC, Powerchip, Hua Hong, Demao , Wuhan Xinxin, Huawei, Holley, Lixin

What is nanofabrication?

Samsung and TSMC are very hot in the advanced semiconductor process. They both want to seize the opportunity in the foundry to win orders. It has almost become a battle between 14 nanometers and 16 nanometers. However, 14 nanometers and 16 nanometers are the two What is the meaning of the number, and which part does it refer to? And what benefits and problems will it bring in the future after shrinking the process? Below we will briefly explain the nanofabrication process.

How tiny are nanometers?

Before we start, it is important to understand what nano actually means. Mathematically, a nanometer is 0.000000001 meters, but that's a pretty poor example, after all, we only see a lot of zeros after the decimal point, but don't really feel it. If you compare the thickness of the nails, it may be more obvious.

If you actually measure it with a ruler, you can know that the thickness of the nail is about 0.0001 meters (0.1 mm). This can be slightly imagined how tiny 1 nanometer is.

After knowing how small the nanometer is, it is necessary to understand the purpose of shrinking the process. The main purpose of shrinking the transistor is to insert more transistors into a smaller chip, so that the chip will not become smaller due to technological improvement. Secondly, it can increase the computing efficiency of the processor; thirdly, reducing the size can also reduce power consumption; finally, after the chip size is reduced, it is easier to fit into mobile devices to meet the needs of future thinning.

Let's come back to explore what the nanometer process is. Take 14 nanometers as an example. The process refers to the minimum size of the wires in the chip that can be 14 nanometers. The picture below shows the appearance of a traditional transistor as an example. The main purpose of shrinking transistors is to reduce power consumption, but which part should be reduced to achieve this goal? The L in the lower left image is the part we expect to shrink. By reducing the gate length, the current can take a shorter path from the Drain end to the Source end (you can use Google to search for MOSFETs if you are interested, there will be a more detailed explanation).

In addition, computers operate on 0s and 1s. How can we use transistors for this purpose? The method is to determine whether the transistor has current flow. When a voltage supply is made at the Gate terminal (green square), the current will flow from the Drain terminal to the Source terminal. If no voltage is supplied, the current will not flow, so that 1s and 0s can be represented. (As for why 0 and 1 are used for judgment, if you are interested, you can go to Chablin algebra. We use this method to make a computer)

Downsizing has its physical limitations

However, the process cannot be reduced indefinitely. When we shrink the transistor to about 20 nanometers, we will encounter problems in quantum physics, causing the transistor to have leakage, which offsets the benefits obtained when reducing L. As an improvement method, the concept of FinFET (Tri-Gate) is introduced. In Intel's previous explanations, it can be known that by introducing this technology, leakage caused by physical phenomena can be reduced.

More importantly, the contact area between the gate terminal and the lower layer can be increased by this method. In the traditional method, the contact surface has only one plane, but after using the FinFET (Tri-Gate) technology, the contact surface will become three-dimensional, and the contact area can be easily increased, so that the Source can be kept at the same contact area. -Drain side becomes smaller, which helps considerably in downsizing.

Finally, why some people say that major factories will face serious challenges when entering the 10-nanometer process. The main reason is that the size of an atom is about 0.1 nanometers. In the case of 10 nanometers, a line has less than 100 atoms. It is quite difficult to manufacture, and as long as there is a defect in one atom, such as an atom falling out or impurities in the manufacturing process, unknown phenomena will occur, affecting the yield of the product.

If you can't imagine this difficulty, you can do a small experiment. Arrange 100 beads in a 10×10 square on the table, and cut a piece of paper to cover the beads, then use a small brush to brush off the beads next to it, and finally make it a 10×5 rectangle. In this way, you can know the difficulties faced by major manufacturers and how difficult it is to achieve this goal.

As Samsung and TSMC will complete the mass production of 14nm and 16nm FinFETs in the near future, both of them want to compete for Apple's next-generation iPhone chip foundry, we will see quite exciting business competition, and will also gain more power saving , Thin and light mobile phones, thanks to the benefits of Moore's Law.

tell you what encapsulation is

After a long process, from design to manufacturing, I finally got an IC chip. However, a chip is quite small and thin, and can be easily scratched and damaged if it is not protected from the outside. In addition, because of the tiny size of the chip, it is not easy to place it manually on the circuit board without a larger size housing. Therefore, this article will describe the packaging next.

There are two common packages at present, one is the DIP package that is common in electric toys, and the black looks like a centipede, and the other is the BGA package that is common when buying a boxed CPU. As for other packaging methods, there are PGA (Pin Grid Array; Pin Grid Array) used in early CPUs or an improved version of DIP (QFP (Plastic Quad Flat Package)). Because there are too many packaging methods, the following will introduce DIP and BGA packaging.

Traditional packaging, enduring

The first thing to introduce is the Dual Inline Package (DIP). The IC chip in this package will look like a black centipede under the double-row pins, which is impressive. This packaging method is the earliest adopted. IC packaging technology has the advantage of low cost and is suitable for chips that are small and do not require too many wires. However, because most of them are made of plastic, the heat dissipation effect is poor and cannot meet the requirements of current high-speed chips. Therefore, most of the chips using this package are enduring chips.

As for the Ball Grid Array (BGA) package, the package size is smaller than that of the DIP and can be easily put into smaller devices. In addition, because the pins are located under the chip, more metal pins can be accommodated than DIP

It is quite suitable for chips that require more contacts. However, the cost of this packaging method is high and the connection method is complicated, so it is mostly used in products with high unit price.

Mobile devices are on the rise, new technologies come to the stage

However, using these packaging methods will consume a considerable amount of volume. Like current mobile devices, wearable devices, etc., quite a variety of components are required. If each component is packaged independently, it will consume a lot of space when combined. Therefore, there are currently two methods to meet the requirements of reducing the size. System On Chip) and SiP (System In Packet).

When smartphones were just emerging, the term SoC can be found in major financial magazines, but what exactly is SoC? Simply put, it is to integrate ICs with different functions into one chip. By this method, not only the volume can be reduced, but also the distance between different ICs can be reduced, and the computing speed of the chip can be improved. As for the production method, in the IC design stage, various ICs are put together, and then a mask is made through the previously introduced design process.

However, SoCs do not only have their advantages. To design a SoC requires a lot of technical cooperation. When the IC chips are packaged separately, each has an external protection package, and the distance between the IC and the IC is relatively far, so there is no mutual interference. But when all ICs are packaged together, the nightmare begins. IC design houses need to change from the original design of ICs to ICs that understand and integrate various functions, increasing the workload of engineers. In addition, there are also many situations, such as the high-frequency signal of the communication chip may affect the IC of other functions.

In addition, the SoC also needs to obtain the IP (intellectual property) authorization of other manufacturers in order to put the components designed by others into the SoC. Because making a SoC requires obtaining the design details of the entire IC to make a complete mask, which also increases the design cost of the SoC. Some people may question why not design one by yourself? Because designing various ICs requires a lot of knowledge related to the IC, only a company with a lot of money like Apple has the budget to poach top engineers from well-known companies to design a brand-new IC. It is better to authorize through cooperation than to do it yourself. R&D is more cost-effective.

Compromise, SiP emerges

As an alternative, SiP jumped onto the stage of integrated chips. Unlike SoC, it buys ICs from various companies and packages these ICs for the last time, so the step of IP authorization is omitted and the design cost is greatly reduced. In addition, because they are separate ICs, the level of interference with each other is greatly reduced.

The most famous product using SiP technology is the Apple Watch. Because the internal space of the Watch is too small, it cannot use traditional technology, and the design cost of the SoC is too high, so SiP has become the first choice. With SiP technology, not only can the volume be reduced, but also the distance between each IC can be shortened, making it a feasible compromise.

After the packaging is completed, it will enter the testing stage. At this stage, it is necessary to confirm whether the packaged IC is functioning normally. After it is correct, it can be shipped to the assembly factory to make the electronic products we have seen. Among them, the main semiconductor packaging and testing companies are Ankor, Xingke Jinpeng, J-devices, Unisem, Nepes, ASE, Licheng, Nanmao, Qibang, Jingyuan Electronics, Fumao, Lingsheng Precision, Sipin, Changdian, Youte

At this point, the semiconductor industry has completed the entire production task.