How to Calculate the Inductance of PCB Trace

Inductance is the property of an electrical conductor that opposes a change in current flow. Every conductor has some amount of inductance associated with it. In printed circuit boards (PCBs), the metal traces that connect components act as conductors and therefore also exhibit inductance.

The inductance of a conductor depends on its physical dimensions and shape. For PCB traces, factors like trace length, width, thickness, and proximity to ground planes or other traces impact its inductance. When high frequency signals flow through a conductor, its inductance can cause effects like signal delay, cross talk, and electromagnetic interference. Therefore, being able to accurately calculate the inductance of PCB traces is important in high frequency PCB design.

In this article, we will explore the basics of inductance, look at the key factors that determine PCB trace inductance, go through some popular inductance calculation methods, and also learn how to use inductance calculators.

Basics of Inductance

Inductance is measured in the unit of Henry (H). The amount of inductance a conductor has determines how much voltage gets induced when current through it changes. From Faraday's law of electromagnetic induction:

V = L * (di/dt)        

Here:

• V is the voltage induced (in Volts)
• L is the inductance (in Henrys)
• di/dt is the rate of change of current flow (in Amps/second)

We can think of inductance as inertia to current flow. The greater the inductance, the more voltage gets induced for a given di/dt through the conductor.

Every conductor has some amount of self inductance (L) - even a straight wire. But inductance gets strongly influenced by the conductor's length and shape. Anything that results in increased magnetic flux linkage increases inductance. Factors like number of turns/loops, coil diameter, proximity to other conductors etc. impact inductance.

Mutual Inductance

When two conductors are arranged such that current flow in one induces voltages in the other, it results in mutual inductance between them.

M = L1 * L2        

Here L1 and L2 are self inductances of the two conductors and M is their mutual inductance. The equation shows that mutual inductance gets larger as self inductances increase.

In PCBs, adjacent traces running in parallel for significant lengths can result in noticeable mutual inductance. But calculating self inductance of individual traces itself can get quite complex. Next, we look at what makes trace inductance calculation difficult.

Challenges in Calculating PCB Trace Inductance

Compared to components like inductors, capacitors or resistors, accurately calculating inductance of PCB copper traces is hard for several reasons:

1. Complex Trace Shapes and Layouts

PCB trace lengths, widths and proximity to plane layers vary a lot depending on routing requirements. Traces bend and turn at different angles. There can be branching traces, vias, intermittent ground planes or splits. Modeling the magnetic flux behavior accurately gets very hard.

2. Impact of Nearby Traces

Adjacent traces act as return paths and alter flux linkages. Even traces on inner layers impact surface trace inductance. The mutual inductance effects are complex.

3. Effect of Dielectrics

The dielectric material that separates trace and reference planes impacts flux fields. Common PCB laminates have dielectric constants (Dk) ranging from 3 to 4. But newer high speed dielectric materials have much lower Dks. Each material impacts inductance differently.

4. Frequency Dependence

A trace's inductance actually varies with frequency - it is not a fixed value. Skin effect and dielectric losses cause the effective inductance to increase with frequency. Simple inductance models do not capture this.

Let's take a closer look at what physical characteristics actually determine a PCB trace's inductance.

Factors That Determine PCB Trace Inductance

For a rectangular PCB trace cross section as shown above, following factors primarily impact its self inductance:

1. Trace Length

Inductance increases linearly with trace length. At higher frequencies, current crowds towards trace edges due to skin effect. This makes the linear inductance-length relation slightly nonlinear.

A trace's length also impacts the amount of mutual inductance with adjacent traces. Longer the parallel run, higher the coupling.

2. Trace Width

Narrower traces concentrate flux lines closer and hence increase inductance per unit length. For a rectangular conductor, inductance per unit length can calculated as:

L' = (μ0/π) * (1/w + 0.5 + ln(2h/w))        

Here:

• L' is inductance per unit length
• μ0 is permeability of free space
• w is trace width
• h is trace thickness

Inductance therefore reduces as trace gets wider in relation to its thickness.

3. Trace Thickness

Thickness by itself does not effect inductance much if width is held constant. Thicker traces are preferred at high currents to reduce resistive losses.

But thicker traces also increase dielectric thickness to reference plane. This slightly increases inductance, but the effect is usually negligible.

4. Separation from Ground Plane

Proximity to a ground plane reduces inductance by providing a closeby current return path. But it increases capacitance to the plane. Both these factors get complexly interdependent at high frequencies.

Traces passing through splits in ground/power planes exhibit increased inductance in the slot regions.

5. Dielectric Material

Dielectrics alter inductance in multiple ways. The relative permeability (μr) directly changes the flux density. Changing dielectric thickness to reference planes alters field distributions. Dielectric losses also increase effective inductance at higher frequencies.

With so many factors involved, calculation inductance accurately gets very tricky. Multiple modeling methods exists to estimate inductance, with varying complexity and accuracy.

Common Methods to Model PCB Trace Inductance

Over the years several analytical, empirical and numerical modeling methods have been developed to calculate trace inductance. Here are some of the popular approaches:

1. Simple Analytical Equations

Some common approximated equations used to estimate inductance are:

Straight wire inductance:

L = (μ0/π) * ln(2h/w)        

Rectangular trace inductance per unit length:

L' = (μ0/π) * (1/w + 0.5 + ln(2h/w))        

Coaxial cables inductance per unit length:

L’ = μ0/2π * ln(D/d)        

Here μ0 is permeability of free space, w = width, h = thickness, D = cable diameter, d = conductor diameter.

While easy to use, these analytical approaches involve many simplifying assumptions about field distributions and current flow. They provide decent estimates but have limited accuracy.

2. Rosa-Neumann Expressions

By breaking up traces into filamentary rectangular loops and summing their inductances, slightly better approximation is achieved. But this still assumes independent flux linkages between loops which is not fully correct.

Increasing number of segments improves accuracy but gets computationally intensive. This method also cannot account for changing shapes along trace lengths.

3. PEEC Methods

Partial Element Equivalent Circuit (PEEC) methods discretize conductors into smaller segments. Each segment gets represented by equivalent RLGC circuits based on its shape, proximity etc. All partial inductances are then combined to compute total inductance.

By better modeling electromagnetic interactions between segments, PEEC achieves good accuracy. But the number of circuits rises rapidly for complex shapes, making it time consuming.

4. Finite Element Methods

FEM is the most comprehensive technique for trace inductance calculation. The trace geometry gets divided into a mesh of small elements. Electromagnetic field equations are then numerically solved to determine currents and flux linkages across the mesh elements.

By using a fine enough mesh, very high accuracy solutions are possible. But the computation cost also grows prohibitively with complexity. So FEM is generally used just for smaller critical trace sections.

5. FastHenry / Q3D

Tools like FastHenry and Ansys Q3D specialize in combined circuit-field simulation of inductance. They utilize clever optimizations like grid scaling, adaptive meshing etc. to reduce the computational overhead of FEM, while retaining accuracy.

If familiar with using field solver tools, these can provide accurate trace inductance values without becoming too time consuming for larger designs.

Now we look at how to easily estimate inductances using some online tools.

Using Inductance Calculators

For quick back-of-the-envelope inductance calculations, online calculators and mobile apps provide a convenient option:

Inductance calculators allow entering trace dimensions and shape to automatically output an estimated inductance value.

Underlying formulas would generally be based on either simple analytical equations or rough empirical approximations calibrated against measured data.

While absolute accuracy is lower compared to field solvers, online calculators do provide decent ballpark inductance estimates quickly. They are handy for doing first-cut analyses or sanity-checks during layout.

Using calculators before a detailed field solve can also help optimize simulation settings best suited for the geometry type. This further improves overall design flow efficiency.

Some good inductance calculator tools to try out include:

• PCB Toolkit
• EMC FastPass
• SpinCAD Designer
• Murata Inductance Meter

We will next see some example calculations for different PCB trace shapes.

Example Inductance Calculations

Let's calculate inductances for common conductor geometries like straight wires, rectangular traces and transmission lines:

1. Straight Wire Inductance

• Round wire with diameter 0.5 mm (w = 0.5 mm).
• Wire length (l) = 15 mm.

Plugging values into straight wire inductance equation:

L = (μ0/π) * ln(2l/w)
    = (4π 1e-7) * ln((2 * 15 mm)/0.5 mm) 
    = 3.67 nanoHenrys        

2. Rectangular Trace Inductance

• Trace: w = 0.254 mm , h = 0.035 mm
• Trace length: 50 mm
• Dk of PCB material = 4.2
• Separation from Gnd (t) = 1.6 mm

μ = μ0 * μr = 4π 1e-7 * 1 = 4π 1e-7   (μr = 1 for air)

L' = (μ/π) * (1/w + 0.5 + ln(2h/w))  
    = 2.64 nH/mm

Total trace inductance over 50 mm  
    = L' * l = 2.64 * 50 = 132 nH        

3. Stripline Inductance

• Stripline trace suspended between two GNDs
• Trace width (w) = 0.5 mm
• Trace thickness (t) = 0.035 mm
• Trace length (l) = 10 mm
• Dielectric thickness (H) = 0.2 mm
• Dk = 3
• Strip spacing (s) = 1 mm

Stripline inductance per unit length:

L’ = (μ0/π) * 0.5 * ln[4H / w + t) * (1 + πs / 4l)]   
    = 25 pH/mm

Total inductance over 10 mm  
    = L' * l = 0.25 nH        

These examples give an idea of how inductance values can vary widely depending on trace shapes and dimensions. Let's now look at some best practices to manage trace inductances.

Design Guidelines for Managing Trace Inductance

Here are some ways in which trace inductances can be controlled in a PCB design:

• Keep traces short - Long traces have proportionally higher inductance. Use shortest paths between driver and receiver circuits.
• Minimize spacing between traces - Closer return paths result in lower loop inductance. But ensure spacing meets crosstalk requirements.
• Route over continuous ground planes - Uninterrupted ground provides minimum inductance return path. Avoid slots and voids underneath traces when possible.
• Use wider traces - Increases self-capacitance which helps counteract inductive effects. But beware of skin depth issues at higher frequencies.
• Avoid vias in high frequency paths - Each via stub adds inductance. Minimize vias by routing critical traces on one layer if possible.
• Split inductive traces - Long single trace can be split into multiple parallel traces with lower overall inductance. Helps reduce delay and reflections.
• Add termination resistors - Series resistor at line end dissipates reflections caused by trace inductance mismatches.
• Use inverse taper patterns - Makes trace impedance more uniform by counteracting rising inductance at higher frequencies.
• Model key traces - Accurately simulating critical trace inductances early in design process enables better optimization before board fabrication.

Next we look at how to check designed trace inductances using impedance profile graphs.

Verifying Designed Trace Impedances

To confirm if designed trace characteristic impedances and inductance values match target requirements, we can generate impedance profiles using field solvers:

Figure showing simulated impedance profile for a designed PCB transmission line geometry

The Z and L plots clearly display the characteristic impedance and inductance values over frequency. Such impedance profiles help visually check for:

• Impedance stability over required frequency range
• Gradual impedance change indicating controlled transmission line behavior
• Absence of abrupt discontinuities that distort signals
• Verifying designed vs actual values by corroboration with calculations

Generating similar graphical plots for critical traces before and after layout helps assess signal integrity. If deviations are found from ideal target profiles, appropriate corrective steps can be taken like adding line terminations, adjusting spacing to planes etc.

Utilizing field solvers this way enables simulating and enhancing impedance performance even without having access to laboratory test equipment.

We will summarize key takeaways next.

Conclusion and Key Takeaways

Inductance associated with PCB traces can significantly impact signal quality at higher frequencies. With increasing digital and analog signal speeds, having ways to accurately estimate inductances is becoming critical.

To summarize key points from our discussion:

• Inductance makes currents resist change - the faster the current change, the more voltage gets induced.
• Complex trace shapes, proximity effects and frequency dependence make inductance calculation difficult.
• Inductance depends strongly on length, width, thickness and separation from ground planes.
• Various analytical, empirical and numerical modeling methods are available to estimate inductance.
• Online calculators and field solver simulations enable easy first-cut inductance analysis.
• Careful early modeling of inductance helps optimize PCB stackup design and trace routing before fabrication.

Going further, additional topics that could be explored are:

• Methods to measure PCB trace inductance like TDR, LCR meters etc.
• Using inverse taper patterns to control impedance variations
• Modeling of vias and discontinuity effects on inductance
• Investigating surface roughness impact on high frequency conduction losses

With increasing signal frequencies, understanding all aspects inductance becomes vital for minimizing unintended effects like radiation, crosstalk and signal distortion. We hope this article provided a good introduction to analyzing trace inductance during PCB design and layout.

Frequently Asked Questions

Why does inductance matter in PCB design?

At lower frequencies, trace inductances generally do not interfere much since impedances stay low. But as signal edge rates keep increasing with advancing IC fabrication technology nodes, even trace inductances start causing effects like overshoots, ringing, ground bounce and EMI at higher frequencies.

So estimating and budgeting inductances of critical traces becomes necessary to ensure signal integrity in modern high speed PCBs.

How to reduce mutual inductance between parallel traces?

Following techniques can help reduce coupling between parallel conductors:

• Increase spacing between traces
• Route them orthogonally instead of parallel
• Place a ground trace as shield in between
• Interleave the traces (like fingers of two hands)
• Use lower dielectric constant material

Why do wider traces have lesser self inductance?

For a given thickness, wider traces have larger surface area resulting in higher self-capacitance to reference planes. This increased shunt capacitance provides a lower impedance path to counteract inductive voltage changes.

Wider traces also concentrate magnetic flux lines closer to conductor surface. Both factors reduce inductance per unit length.

How does height above ground plane impact inductance?

Reducing distance to the ground reference decreases loop area for return currents. This reduces flux linkages resulting in lower overall partial self inductance.

But decreased spacing also increases parasitic capacitance which boosts electric field densities. So an optimal balance exists for minimizing impedance.

Why do vias increase inductance?

Each via hole forms additional parasitic inductance and capacitance due its length and diameter. So a string of vias can introduce noticeable inductance in series.