HOREXS- Glass substrate

HOREXS team are creating a great things for the semiconductor industry!

?As the demand for AI chip computing power increases, glass substrates are used as substitutes. The complexity of AI applications increases, and the demand for high-density computing, machine learning, parallel computing, and HPC applications in fields such as AI also puts higher demands on chips. Advanced packaging using glass substrates is one of the potential solutions. In September 2023, Intel launched the industry's first glass substrate advanced packaging plan, announcing that it would use glass substrates for advanced packaging by 2030, and Samsung and other manufacturers are also actively following up. At the same time, glass materials have a wide range of applications, including replacing CoWoS-interposer/FC-BGA substrates, co-packaging optical device integration, Mini/Micro LED backplane materials, passive devices, and sensor packaging.

?Glass substrates have outstanding physical properties. Glass substrates have high surface flatness and low roughness, which is conducive to high-density RDL wiring. Excellent chemical stability, can effectively resist environmental erosion such as moisture, acid and alkali. Glass substrates can effectively combat warping problems during packaging. At the same time, it has excellent electrical properties, high resistivity and low dielectric constant can reduce transmission loss, ensure interconnection density and signal integrity. In addition, the change in package size of glass substrate packaging brings significant cost benefits. The mismatch between rectangular chips and circular silicon interposers will lead to waste at the edge of the wafer and further deteriorate the efficiency of use when the chip size becomes larger. Using large-sized rectangular glass as a carrier or ultimately as an interposer can accommodate more chips in one carrier or interposer, which can significantly improve the efficiency of advanced packaging.

?TGV technology is a key technology for achieving vertical electrical interconnection of glass substrates. It involves forming through holes on glass substrates, which is crucial for the thinness and functional integration of electronic devices. The difficult links in the TGV process flow are the two major links of through-hole and hole filling. The technical difficulties of TGV through-holes have been overcome. The preparation of TGV through-holes needs to meet a series of requirements such as high speed, high precision, narrow pitch, smooth sidewalls, good verticality and low cost. Laser-induced etching is currently the most promising process for large-scale use. Laser-induced etching rapid prototyping technology uses ultrafast lasers to modify glass in a directional manner, and then amplifies the modified channel of the glass to form a through hole through subsequent chemical etching, which can realize the production of deep holes or grooves in glass with a high aspect ratio, and has the advantage of isotropic etching. For the glass substrate filling process, the challenge in PVD is how to improve the adhesion between the metal layer and the glass surface.

? The potential of advanced packaging of glass substrates has been discovered, and the glass substrate packaging industry chain has accelerated research and development. In terms of IDM/packaging, Intel announced that it will mass-produce glass substrates in 2030, and has invested $1 billion in the Arizona plant to establish a glass substrate R&D line and supply chain. Samsung has formed a united front of Samsung Electronics, Samsung Display, and Samsung Electro-Mechanics to enter the research and development of glass substrates; in terms of chip design, AMD is actively conducting chip product introduction glass substrate testing; the glass substrate business has matured, and Corning, Asahi Glass, and Schott all have the ability to supply high-precision glass wafers or substrates; in the laser through-hole business, manufacturers such as LPKF and Samtec can provide mature laser through-hole (TGV) solutions.

Glass substrates become the focus of research and have a wide range of applications

As the demand for AI chip computing power increases, glass substrates are replacing it. The complexity of AI applications has increased, and the demand for high-density computing, machine learning, parallel computing, and HPC applications in fields such as AI have also put forward higher requirements for chips. For example, AMD's new generation EPYC processor supports up to 384 threads and up to 192 cores, of which 16 "Zen 5" CCDs (core composite chips) are configured. The CCD chip has advanced manufacturing technology and uses TSMC's 3-nanometer process, while the central I/O chip (IOD) uses a 4-nanometer process, showing the demand for higher chip processes in the context of the AI era. With the gradual increase in AI computing power requirements and the high complexity of hardware circuits, traditional PCB organic substrates and TSV technology may become a shortcoming that restricts the production of high-performance computing chips such as AI chips in the future.

Intel has set off a hot topic, and glass substrate technology has become the focus of the industry. In September 2023, Intel launched the industry's first glass substrate advanced packaging program, announcing the use of glass substrates for advanced packaging by 2030. Intel expects that by the end of 2030, the semiconductor industry may reach its limit of scaling transistors on silicon packages using organic materials. As the demand for more powerful computing increases, the semiconductor industry has entered a heterogeneous era of using multiple "chiplets" in packages, and improving signal transmission speeds, power transmission, design rules, and the stability of packaging substrates will be critical. Compared with the organic substrates currently used, glass substrates have excellent mechanical, physical, and optical properties, which can connect more transistors in the package, provide better scalability, and assemble larger chiplet complexes (SoC, system-level package). Glass substrate technology may be the key to helping Intel expand its goal of 1 trillion transistors on a single package. In early May of this year, Samsung Electro Mechanics announced that it expects to start producing glass substrates for high-end SiP in 2026. At CES 2024 in January, Samsung Electro-Mechanics proposed to build a glass substrate prototype production line this year, with the goal of producing prototypes in 2025 and achieving mass production in 2026. BOE, TSMC, Qunsheng Industrial, AMP Electronics, etc. are also actively exploring glass substrate technology. The expansion speed of advanced packaging capacity is difficult to keep up with the explosive growth demand of AI chips, and advanced packaging using glass substrates is an excellent solution.

Glass materials have a wide range of applications. As an important innovation introduced in the field of packaging, glass substrates provide interposers with similar functions to the silicon interposers in CoWoSS structures, allowing redistribution layers (RDL) and through-glass vias (TGV) to be built directly on glass panels, which is expected to replace FC-BGA substrates in ABF substrates; glass waveguides and TGVs are integrated in co-packaged optical devices (CPO) to achieve higher interconnection density, improve power transmission and signal routing; as a backplane material in Mini/Micro LED display technology, it has good thermal conductivity, low thermal stability and physical deformation, outstanding flatness, and reduces process difficulty and improves yield; glass is also increasingly used in passive device manufacturing, and can become a highly versatile substrate for a wide range of sensor and MEMS packaging applications.

Glass substrates have superior performance and are the first choice for the next generation of advanced packaging

Excellent natural properties make them ideal substrate materials

Glass substrates have outstanding physical properties. Glass substrates have high surface flatness and low roughness, providing an ideal platform for the manufacture of micro-sized semiconductor devices and facilitating high-density RDL wiring. In addition, glass has excellent chemical stability and lower hygroscopicity than organic materials. It can effectively resist environmental erosion such as moisture, acid and alkali, and ensure the long-term stability of components in the package.

Effectively combat warping problems and is suitable for large-size packages. Large-size substrates need to carry high-density chip packaging, and a lot of heat is generated during the chip packaging process. When stacking packages, silicon chips, epoxy molding compounds, and organic RDLs all have different coefficients of thermal expansion (CTE), which means that when the temperature rises, the components of the stack may expand to different degrees. During the molding, curing, or debonding process, the stress at the interface of these materials may change, causing the stack to warp and may cause delamination or joint/bump misalignment.

The thermal expansion coefficient of glass substrates is 3-9ppm/K, which is close to 2.9-4ppm/K of silicon. It is not easy to warp due to different degrees of deformation between layers of materials caused by heat generated during the packaging process. At the same time, its Young's modulus is 50-90GPA, which is significantly higher than that of organic materials, and has stronger resistance to deformation. The large dimensional stability and adjustable rigid modulus of the glass substrate make its through-hole density 10 times that of the original silicon substrate, which improves the chip packaging density.

Superior electrical performance and reduced transmission loss. Glass is an insulating material with a relative dielectric constant of only about one-third of that of silicon wafers. A lower dielectric constant means that it has lower parasitic capacitance, which reduces signal loss during transmission, so the glass interposer can provide better power efficiency or better signal integrity during high-speed transmission. In addition, due to the high resistivity of glass, there is less current leakage between adjacent interconnects, so compared with silicon, glass materials have less crosstalk or noise problems. As interconnects become more and more sophisticated and dense, glass substrates can ensure interconnection density and signal integrity to meet the needs of artificial intelligence chip packaging.

Package size changes bring significant cost benefits. All chips are rectangular, while silicon interposers are round. This mismatch may result in a large amount of unused area at the edge of the wafer, and the efficiency of wafer area use may deteriorate when the chip size becomes larger. If 300mm wafer-level packaging is compared with 515x510mm panel-level packaging, the rectangular panel-level packaging chip occupies 93% of the area, while the wafer-level packaging only occupies 64%. This geometric difference directly leads to a huge difference in production rate during the production process. In addition, according to the Yole report, for example, the area utilization rate of FOWLP technology is <85%, and the area utilization rate of FOPLP is >95%. Therefore, using large-sized rectangular glass as a carrier or ultimately as an interposer can accommodate more chips in one carrier or interposer, which can significantly improve the efficiency of advanced packaging. Specifically, it is estimated that the transition from 200mm to 300mm can save about 25% of the cost, and the transition from 300mm to board level can save 66% of the cost. The cost of panel-level packaging will be reduced by 66% compared with wafer-level packaging.

TGV is the core technology of glass substrates, and HOREXS has mastered the 15:1TGV perforation technology.

TGV (Through Glass Via) technology is a key technology for vertical electrical interconnection of glass substrates. It involves forming through holes on glass substrates, which is crucial for the thinness and functional integration of electronic devices. For various applications in the field of advanced packaging, tens of thousands of glass through holes are usually applied and metalized on each substrate to obtain the required conductivity, which is a key issue restricting mass production. The process flow of TGV includes preliminary preparation, laser drilling, etching, subsequent processing and quality inspection, among which the difficult links are through holes and filling holes.

The technical difficulties of TGV through holes have been overcome. The preparation of TGV through holes needs to meet a series of requirements such as high speed, high precision, narrow pitch, smooth sidewalls, good verticality and low cost. The current mainstream glass through hole processing and forming methods include sandblasting, focused discharge, plasma etching, laser ablation, electrochemical discharge, photosensitive glass method, laser induced etching, etc. Among them, laser induced etching has obvious advantages and is currently the most promising process for large-scale use. Laser-induced etching rapid prototyping (LIERP) uses ultrafast lasers to modify glass in a directional manner, and then amplifies the modified channel of the glass to form a through hole through subsequent chemical etching, which can achieve the production of high-aspect ratio glass deep holes or grooves, and has the advantage of low cost.

Another technical difficulty that limits the application of glass through holes is high-quality metal filling. HOREXS successfully tested the filling of holes in 15:1 TGV perforations. Unlike TSV (Through Silicon Via), TGV has a larger aperture and is mostly through-holes, which takes a long time to electroplate and is costly. On the other hand, unlike silicon materials, due to the smooth surface of glass, it has poor adhesion to common metals (such as Cu), which can easily cause delamination between the glass substrate and the metal layer, resulting in curling or even falling off of the metal layer. The main solutions are TGV metal solid hole filling technology and TGV hole electroplating thin layer technology. The former deposits a seed layer inside the TGV blind hole by physical vapor deposition (PVD), and then electroplates from bottom to top to achieve seamless filling of the TGV. However, for high aspect ratio through-holes, the equipment and process of physical vapor deposition are too expensive. The TGV in-hole electroplating thin layer technology uses a thin layer electroplating solution inside the through-hole instead of solid electroplating to achieve electrical connection. In terms of electrical performance, the insertion loss of the two is slightly different, but thin layer electroplating can effectively reduce electroplating time and electroplating costs.

The potential of advanced packaging of glass substrates has been discovered, and the glass substrate packaging industry chain has accelerated research and development. In terms of IDM/packaging, Intel announced that it will mass-produce glass substrates in 2030, and has invested $1 billion in the Arizona plant to establish a glass substrate R&D line and supply chain. Samsung has formed a united front of Samsung Electronics, Samsung Display, and Samsung Electro-Mechanics to enter the research and development of glass substrates; in terms of chip design, AMD is actively testing the introduction of chip products into glass substrates; the glass substrate business has matured, and Corning, Asahi Glass, and Schott all have the ability to supply high-precision glass wafers or substrates; in the laser through-hole business, LPKF, Samtec and other manufacturers can provide mature laser through-hole (TGV) solutions.

The domestic glass substrate packaging industry chain is complete. Glass substrate packaging manufacturers including Changdian Technology, BOE, Tongfu Microelectronics, Shenzhen Tianma, HOREXS, etc. are continuing to make efforts to overcome them, and we look forward to their further good news.