History of ISIJU-1
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ISIJU History: Development of an Indigenous Second Generation Digital Computer by Indian Statistical Institute (ISI) and Jadavpur University (JU)
Dr. L. N. Goyal, Dr. Santanu Das & Dr. Pradip K. Das
(Originally written on October 30, 2021)
Table of Content
I. Introduction
II. Genesis of ISIJU
III. ISIJU Team
IV. ISIJU Architecture
V. Comparison of ISIJU with the Other Contemporary Machines
VI. ISIJU Circuits & Components
VII. Conclusion
VIII. Acknowledgement
IX. References
X. Appendix: Biographies of Key Members of ISIJU Project
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I. Introduction
Project ISIJU-1 was conceived in the year 1961 for building a second-generation (transistorized) digital computer with following objectives:
Majority share of the funding (60-70%) was to come from Indian Statistical Institute (ISI), situated on B. T. Road in the northern fringe of Calcutta and the rest from Jadavpur University (JU). The work was carried out at the then Department of Tele-Communication Engineering (renamed as Department of Electronics and Tele-Communication Engineering (ETCE) in 1964), Jadavpur University. It was also decided that ISI would depute a few of their staff members to work in the project.
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Prof. Jnan Saran Chatterjee, Head of the Department of Electronics and Telecommunication Engineering, was appointed to lead the project from JU and Prof. Samarendra Kumar Mitra similarly headed the project from ISI.
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Dr. Biswajit Nag, who had joined as a lecturer in the ETCE department, JU after obtaining his M. Tech in Radio Physics and Electronics from Calcutta University in 1955, was asked to provide the day-to-day supervision of the project at JU. Prior to this, Dr. Nag had a brief stint at ISI where he worked under Prof. Samarendra Kumar Mitra. Earlier, Dr. Nag worked as a Research Scholar at Manchester University under the Commonwealth scholarship. There he worked on Atlas Computer - one of the world's first supercomputers.
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The Architectural Design and Software team was led by Professor Ambarish Ghosh of ISI along with Mr. Prabhat Kumar Mitra and E. V. Krishnamurthy - also from ISI.
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The hardware team was led by Professor Asish Kumar Sen of ISI along with his junior colleagues from ISI. A number of JU Research Scholars, Lecturers, and other employees also were part of the hardware team.
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Dr. Biswajit Nag, who was a hands-on researcher, was responsible for the logic design and implementation of the main memory systems which was based on magnetic core.
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ISI at that time had UN funding, mainly for manpower, and the same was utilized to bring in experts from abroad to work with the ISIJU team. One such expert was Richard Aschenbrenner from Argonne National Laboratory, USA. He used to stay in the guest house of ISI and commute to JU and back every day – a distance of approximately 20 km each way through the heart of the city. Mr. Aschenbrenner designed the logic for the control of the Auxiliary memory system based on magnetic drum.
Mr. Asish Sen, who led the hardware efforts, spent 4 years in the UK and worked in various establishments like English Electric, Leo and Marconi. He played a leading role in designing and implementing the hardware machinery of ISIJU.
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Mr. Prabhat K Mitra, who was deputed from ISI to JU to lead software efforts, held a Master's degree in Applied Mathematics from Calcutta University and was a permanent employee of ISI. In addition to leading the software team, he also made very valuable contribution to the architectural design of the machine collaborating with Dr. Ambarish Ghosh and Dr. E. V. Krishnamurthy.
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As mentioned earlier, a number of research scholars from JU also contributed to the hardware design of the machine. They were all selected in different years by Dr Biswajit Nag to work under him mostly for their master's projects. Their brief biographies are discussed in the next section (ISIJU Team).
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The machine was organized on a character basis, a character consisting of 6 alpha-numeric bits, one word marker bit and one parity bit.
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The operational memory was based on the use of magnetic cores and had a 6-μsecond cycle time. It was constructed in a stack of 4096 characters each. 8 such stacks consisting of 32K characters formed a bank. Any character in any stack of a bank was addressable by a 15-bit address. A number of such banks could be incorporated to ensure that the computer has the requisite amount of main memory. The plan was to support FORTRAN and ALGOL programs.
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As mentioned earlier, the machine had a magnetic drum as a backup (Auxiliary) memory.
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For input and output, 5-to-8-hole paper tape reader and punch were used. A 7-track Flexowriter, especially designed for the machine, was used for program tape preparation and editing. All peripheral devices communicated autonomously with the core memory through 12 autonomous channels.
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The machine was quite fast considering the technologies available readily in those days. For instance, the solution of linear equations involving 40 unknown parameters took around 1 minute.
II. Genesis of ISIJU
The Report below was published by ISIJU Joint Computer Project Committee on the occasion of the inauguration of Computer ISIJU-1 [Commissioned by Shri M. C. Chagla, Union Minister of Education on April 2, 1966])
Report on the ISIJU Computer Project Committee on the Computer ISIJU-I
The computer, though not yet twenty years old, has already made a great impact on the modern technology and, perhaps, on the future course of human civilisation by ushering in the Age of Automation. Even a small developing European country, like Greece, had 50 computers in 1964 and 30 more were on order, whereas there are now scarcely sixty computers all over India. With the declared objective of rapid industrialisation, it is inescapable that India will have to enter the computer era now or in the very near future. A modern industrial society without extensive use of computer looks somewhat like a Newcommen's Atmospheric Engine powered by a Nuclear Reactor. It was plain to the Indian Statistical Institute and Jadavpur University, the two participating institutions, that the technical know-how of computers must be built up in the country, and a nucleus of highly trained personnel in this new and very rapidly developing technology has to be created quickly. With this objective in view the two institutions undertook the project of building two modern solid state computers suitable for large data processing work and scientific computation alike. The soundness of the enterprise was proved soon after the project was launched, as a number of academic institutions and business organisations in the public and private sectors began to realise the importance of computers and placed orders for computers from manufacturers abroad.
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Management of the Project
The work was started in 1961 under a joint project of the Indian Statistical Institute and Jadavpur University for building two solid state general purpose digital computers. The joint project was formally approved by Jadavpur University and the Council of the Indian Statistical Institute later.
A high-powered body with delegated authority called the ISLIU Joint Computer Project Committee was constituted for looking after the management of the work of building the two computers. The Project was formally inaugurated in October 1961, though the actual work was started about six months later when the working team could be formed. But in October 1962, the project suffered a very serious set-back due to the declaration of National Emergency and its economic consequences. The project had to be postponed almost at its very birth. However, towards the beginning of 1964 things looked better and the project could secure the necessary import licences through the University Grants Commission for importing the essential components for the construction of the first machine. Work was resumed but its progress was constantly falling short of expectation, hampered as it was by funds being not readily available during the last two years. Ultimately, however, thanks to the enthusiasm, devotion and diligence of the young people actually engaged in the work, it has become possible for the first computer to appear within the estimated period of time.
The Computer
Unlike the computer called the TIFRAC constructed by the Tata Institute of Fundamental Research based on early valve circuits, this computer uses solid state electronics and has some characteristics which are not found even in much larger and more expensive computers commercially available in the world market at present. The computer, though much faster and more versatile than any computer so far installed in India, excepting the large Control Data Corporation Computer, the CDC 3800, purchased by the Atomic Energy Commission and installed at the Tate Institute of Fundamental Research, suffers a little for want of an essential equipment, the line-printer. The acute foreign exchange position and paucity of funds due to curtailment of government grants have made it impossible to procure a suitable line-printer. It will be added as soon as funds are available.
The first computer which has been completed is technically called ‘Character-oriented'. This philosophy has been accepted in the popular American computers such as the IBM 1620, IBM 1401, the RCA 301 and in the more recent British made computers, the English-Electric Leo-Marconi System 4 series. Though this design philosophy introduces extra complexities in the control unit and seriously affects the speed of operation, it has some advantages. One advantage is that the length of a 'word’ can be varied at will, which makes it possible to operate with numbers of any length. This is an advantage in all data processing work and in many scientific problems. This also makes mechanical translation from one language to another much easier and efficient. In this machine a character is composed of eight binary digits, one of those is the ‘parity bit’ which controls any mistake during the transmission of a 'word' from one unit to another, and the other is called the 'tag bit' which marks the end of a ‘word’. The remaining six ‘bits’ represent the actual character, which may denote any of the ten decimal digits 0 to 9, or any of the twentysix Roman alphabets, a to z, and some other symbols like punctuation marks. In all sixtyfour different characters: can be represented by those six bits. These six bits can also represent a six digit binary number. All arithmetic operations can be performed in decimal as well as in binary scale with variable word-length as desired by the programmer. This is a unique feature which is not found at present in any commercially available machine. Though the speed of calculations has been stepped up considerably, the control unit has become much complicated and the designers had to break new grounds for achieving this object. The machine, though much smaller, has the features of larger machines, viz, time-sharing by the input and output units and the ability to accept a number of different peripheral units. The instruction code has been designed specifically with a view to making the writing of compilers, such as ALGOL 60 and FORTRAN, easier. Some more details of the machine are given in the last paragraph.
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The Working Team
The credit for the success of this complex and challenging engineering project goes entirely to the excellent team of able and energetic young men from the Indian Statistical Institute and Jadavpur University, who worked hard joyfully in a spirit of mutual understanding and co-operation. It is worthy to note that the entire design and construction was completed from scratch by this batch of young engineers and scientists, none of whom had ever been associated with the actual designing of a computer and they had to learn the science and art of designing and building a sophisticated computer all by themselves by reading books and journals. Some of these are students of Jadavpur University working for their Master's degree in Electronics and Telecommunication Engineering. The availability of these bright, enthusiastic and young people, guided by their teachers young like themselves, and seriously interested to apply the knowledge they are acquiring, is one of the secrets of success of this Project. The potentialities of young graduates, if properly directed, are yet to be appreciated and recognised in the higher scientific and technological circles in the country.
Sitting (L to R) - A. K. Sen, P. K. Mitra, A. Ghosh, K. Das, A. Roy, S. Sen, E. V. Krishnamurthy, B. Nag
Standing (L - R) – A. Ghosh, K. Shantikumar, R. Sengupta, B. Maulik, G.K. Biswas, S. Das, M. K. Chakraborti, D. K. Basu (?), L. N. Goyal, N. R. Ganguly, B. Mukherjee, N. K. De
On Leave – C. L. Narasimhan (?), R. Krishna, J. Sarma (?)
The Task for the Future
The first computer culminates the first phase of the Joint Project. There is a big question mark for the second computer. Originally the intention was to build a fully parallel computer comparable in speed to the large commercially available computers. More than Rs. 3 lacs of foreign exchange will be required to import the essential components. which is not forthcoming. The design work of the second computer has been taken in hand, but its physical realisation depends on the availability of funds and particularly of the foreign exchange component. But, till the second computer goes into operation, the ISI users will be able to make full use of this first computer directly from the ISI Computing Centre at Baranagar through a micro-wave data-link to be provided shortly. There is, however, a great need for smaller computers at present. An electronic desk calculator, if properly designed, can be expanded into a small computer, suitable for most scientific and business applications in the country. Most of the components for such a calculator are manufactured in the country now. The cause of dissemination of the computer knowledge and of computer education, which was the underlying objective of the Joint Project, cannot be better served it inexpensive computers can be made available in the country without foreign assistance and spending of very limited foreign exchange. The Joint Project Committee's task will only be fulfilled when this is realised.?
The other task, by no means less important, is computer education. The computer is not only an instrument for rapid and complex calculations but a versatile tool of science with possibilities of application to diverse fields which are not yet fully explored. This aspect is very important in India where the computer has been introduced only very recently. This home-made computer will be ideally suited for this purpose.
III. ISIJU Team
The Joint ISIJU team was organized as shown in the organization chart below. The JU team reported to Dr. Jnan Saran Chatterjee who was the Head of the Department of Electronics and Tele-Communication Engineering at Jadavpur University.?
The ISI team reported to Prof. Samarendra K Mitra who partnered with Dr. Jnan Saran Chatterjee in managing the team.
Dr. Triguna Sen was the Rector of Jadavpur University at that time and Dr. Prasanta Chandra Mahalanobis was the Director of Indian Statistical Institute. Both of them were very supportive of this collaboration between the ISI team and the JU team and without their active efforts, the funding for the project could not have been secured.
Dr. Biswajit Nag, Professor of Electronics and Tele-Communication Engineering at Jadavpur University led the JU team while Prof. Asish Sen and Prof. Prabhat K. Mitra led the ISI team.
The day-to-day administration of the project was managed by Prof. Biswajit Nag who was assisted by Mr. Gour Kishore Biswas and Mr. Nirmal Kumar De both of whom were deputed to the team by ISI.
As mentioned earlier, Prof. Biswajit Nag designed the memory system of ISIJU-1 and Prof. Asish Sen, assisted by others, implemented the CPU, Paper Tape Reader (input), and the Paper Tape Punch System (output). Prof. Prabhat K. Mitra was in charge of writing micro codes for implementing the CPU logic and he used to lead the entire software team of the project.?
Please refer to Section IV for the architecture diagram of ISIJU-1.
Dr. Mihir K. Chakraborty is a 1963 Calcutta University Radio Physics graduate. He joined ISIJU Project in 1963 being deputed by ISI to the project. He left for the UK in 1967 for Doctoral studies at Leeds University and then came back to join ISI in 1970. He held several positions in ISI, including the post of Professor and Dean.
Mr. Nihar Ganguly graduated from JU Electronics and Tele-Communication Engineering department in 1961 and joined the Electronics department of ISI. He was at ISI till his retirement.
Dr. Mihir K. Chakraborty and Mr. Nihar Ganguly designed along with others some of the key circuitry of the machine. They were also responsible for laying out and implementing the logic circuits in Vero boards [4,5].
Prof. Biswajit Nag recruited some of his students from Electronics and Tele-Communication Engineering at Jadavpur University as members of the technical staff. It started with Krishna Rallapalli (JU, 1962). Mr. Rallapalli went to Australia in 1965 and then moved to USA where he was a key member of Digital Equipment Corporation's Engineering team.
Dr. Lakshmi N. Goyal (JU, 1963) joined the team in 1963 and worked very closely with Prof. Prabhat K Mitra in Designing the Arithmetic and Logic Unit of the machine. Dr. Goyal left for the USA in 1967 to join University of Illinois in Urbana-Champaign to finish his PhD in EE. Dr. Goyal then joined BELL Laboratories in New Jersey, USA from where he retired a few years back.
Dr. Dipak K. Basu (JU, 1964) joined the team in 1964 and worked very closely with Prof. Asish Sen and architected the console logic. Dr. Basu completed his PhD from JU and became a teaching staff member of the Electronics and Tele-Communication Engineering at Jadavpur University in 1968. In JU, he devoted his time to research in various disciplines and guiding PhD students, some of whom are now occupying eminent positions in academia and industry. Dr. Basu visited several institutions in Germany a number of times as Alexander von Humboldt
Fellow between mid-1970's and mid-1980's. Dr. Basu was an AICTE Emeritus Fellow in the Computer Science and Engineering Department, Jadavpur University, for three years from 2008 to 2011.?
Dr. Santanu Das joined the team in 1965 and assisted Prof. Asish Sen in commissioning the CPU, and the I/O units. Dr. Das became a lecturer at the Electronics and Tele-Communication Engineering at Jadavpur University in 1968 and then left for the USA in 1969 to join the Computer Systems Lab of Washington University, St. Louis. He completed his D.SC in 1973 and worked for ITT corporation for 14 years before starting a company developing and marketing microchips for communication applications. He now lives in Connecticut, USA.
Dr. Mohit Kumar Roy obtained his MSc degree in Applied Mathematics from the University of Calcutta, He joined ISI, Kolkata and subsequently joined the ISIJU Project during 1963-64 and got associated with Prof. Samrendra Kumar Mitra, Prof. Prabhat Kumar Mitra, Prof. Biswajit Nag, amongst others. After a brief stint at ICL Limited, he joined the Computer Centre of the Department of Electronics & Tele-Communication Engineering at Jadavpur University in 1968 to teach PG Diploma course in Computer Science. Roy got his PhD in 1978 on data structures. On deputation, he spent a few years at the Regional Computer Centre, Kolkata in the early days of Burroughs 6738 system before joining as Professor of Computer Science at Jadavpur University.
Prof. Swapan K. Ray joined the team in 1969 and led the ISIJU-1 engineering efforts for a number of years. He then joined the Computer Science Department of JU as a teaching staff member and devoted his time in teaching and research. Prof. Ray spent 1 year at Brooklyn Polytechnic in New York as a Fulbright Scholar before returning to JU. At JU, he guided a number of PhD students some of whom are now occupying eminent positions in academia and industry.?
Dr. Rana Dattagupta joined the ISIJU team in 1967 and collaborated with Dr. Santanu Das in refining the logic design of the Auxiliary Memory System (Magnetic Drum). He later on was in charge of implementing the Auxiliary Memory System. Dr. Dattagupta completed his PhD from JU and then went to the UK with a scholarship to complete a second PhD. Dr. Dattagupta was a teaching staff member at the Electronics and Tele-Communication Engineering at Jadavpur University for many years.?
Two other notable contributors were Dr. Debabrata Ghosh Dastidar and Mr. Ajay Kumar Majhi. Both of them initially joined as programmers in the ISIJU project and later became members of the teaching staff at the Electronics and Tele-Communication Engineering.
Dr. Pradip K. Das joined Dr. Biswajit Nag in 1968 as a Master of Engineering (ME) student and led a number of projects reporting to Dr. Biswajit Nag. He was not directly associated with the ISIJU team. Instead, he was involved in other projects reporting to Dr. Nag. Some of the notable ones were an Electronic Calculator in collaboration with BEL (Bharat Electronics Limited, Bangalore) and a new computer following the architecture of Digital Equipment Corporation's (DEC) PDP-11 both using integrated circuits. Dr. Pradip Das was a teaching staff member at the Electronics and Tele-Communication Engineering at Jadavpur University for many years. Dr. Das spent a number of years at the Queen's University of Belfast, UK, on study leave from JU.
IV. ISIJU Architecture
1. Introduction:
In the design of the Computer the following factors have been taken into account :
In the actual hardware design emphasis has been laid on the reliability of the machine, ease of maintenance and flexibility i.e., the facilities in the system for taking up small as well as large configuration. In the systems and algorithm design a number of interesting and novel features have been incorporated in the machine with the object of increasing its overall power as a general-purpose computer. The resulting complexity in the micro-operations of the computer has been tackled through the use of advanced micro-programming techniques. The design has been made flexible enough to incorporate any new functions or modify existing code at any time.
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2. Systems Configuration:
The machine in organised on a character basis, a character consisting of 6 alpha-numeric bits, one word-marker bit and one parity bit.
The operational memory consists of a magnetic core of 6μs cycle time. It is constructed in stacks of 4096 characters each. Eight such stacks consisting of 32K characters form a bank. Any character in any stock of a bank is addressable by a 15-bit address. Although a number of such banks can be attached to the CPU (Central Processor Unit), one bank in considered to be adequate for compilation of ALGOL or FORTRAN programmes, because of the powerful order code chosen for the computer.
The machine has magnetic drums as back-up memory and magnetic tapes or discs for file work.
Note 1: The APM was a 16-bit 32word linear memory.
Note 2: Console had the highest priority.
Note 3: Paper Tape Punch had the lowest priority.
Note 4: APM had designated words corresponding to the devices seeking access to the memory pointing to where the device should transfer information to or from.
For input and output, 5 to 8 hole paper tape reader and punch, 80-column card reader and punch, 120-column on-line printer can be used in any combination.
A 7-track-Flexwriter, for which the specifications for the symbol set, the tape codes and editing facilities have been especially designed by the manufacturer for the machine is used for programme tape preparation and editing. A Console Flexowriter of similar specifications will be used for operator intervention during programme run.
All peripheral devices including the Console Flexowriter communicate with the core memory automatically through 12 data channels on a fully time-shared basis. Mechanisms can be linked to each channel upto a maximum of 8.
3. Data Format:
In the machine a number or an alpha-numeric string may consist of a variable number of characters, the end of a number or string being indicated by the presence of the word-marker bit in the most significant character.
A number N has the floating point representation ____(???)____ where C is mantissa and N is the characteristic of the number, B is 2 for binary representation and 10 for decimal representation.
The machine performs arithmetic operations on both binary and binary-coded decimal numbers, the former for scientific computations and the latter for data-processing work.
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A binary mantissa may consist of a variable number of characters, each character consisting of 6 bits of the binary string. A mantissa can be shifted by characters only, i. e., in multiples of 6 bits only, so that the effective base of a binary number in 26 or 64. The exponent character consists of one character only, holding the binary value from -32 to +31. Thus the range of binary values which can be held in one word of the machine is ______(???)_____. In the case of decimal numbers, each decimal digit is held in one character and the exponent is held in one character, having the range -9 to +9.
Negative mantissa and exponent are represented in complement form. It is __(???)___ complement in the case of binary numbers and ___(???)___ complement in the ease of decimal numbers. The most significant bit in the most significant character is the sign bit. It has the value 1 for negative numbers and 0 for positive numbers.
4. Instruction Format:
Like data, instructions also have variable formats. There are single-address as well as double-address instructions, consisting of from 4 to 8 characters.
A single-address instruction consists of 4 characters : I character for the Op-code and 3 characters to specify the Index register address and the Operand or Jump address.
All type of addressing, i. e., direct, indirect and immediate (i. e. programme constant) addressing so possible, and each type of address is index modifiable. In the case of indirect address with a modifier, the indirect address is first replaced by the content, which is then modified by the content of the Index register. An indirect address can also be modified before replacement by the use of a special instruction called ‘Pre-modification’.
There are 31 index registers - all located in a fixed area of the core memory and each consisting of 3 characters.
Arithmetic and logical instructions are single-address instructions, which use an accumulator for storing one of the operands and the result. Because of the variability of word-lengths, however, the accumulator is also located in the core memory and its position for a given set of arithmatic and logical instructions man be pre-set anywhere in the memory by a special instruction.
There are two types of peripheral instructions - one for I/O (Input/Output) operations and the other for auxiliary memory (dru, tape or disc) transfer operations. Each type uses the same instruction format for different channels and mechanism numbers. These are 8-character long double address instructions.
The instruction repertoire can be divided into the following classes :-
5. Special Features
As mentioned before, the computer, as compared to machine of similar kind, has a number of interesting and novel features, among which the following may be mentioned :
(a) Experience shows that for any computer installation, it is hardly possible to restrict its use to only scientific-research or to only commercial data-processing work. The ISIJU computer, being able to perform operations on both binary and decimal numbers will, no doubt, go a long way in meeting both these requirements efficiently.
(b) It can perform arithmetic operations in both generalised fixed point and significant digit floating point modes. In the first mode the programmer can pre-set the number of decimal (or binary fractional) places upto which he may like his computations to be performed. In the second mode, the results of arithmetic operations, particularly multiplication and division, are given upto as many characters as may be correct. For example, if a four-character long number is multiplied or divided by a six-character long number, then the product or the quotient is given in the accumulator as a four-character long number. In the case of multiplication, the ten-character long double length product is also given in a double-length product register, so that it can be used by the programmer, if necessary.
(c) If, as a result of addition or subtraction, there is a loss of significant figures, the word-marker is brought down to the resulting most significant character, thereby cutting out the non-significant zeros. This feature has two very important consequences : first, information about the loss of precision in the result is retained, and secondly, because of the cutting out of redundant zeros. subsequent arithmetic operations on the number are performed on lesser number of digits, thereby speeding up subsequent arithmetic operations. This saving in time becomes particularly significant in multiplication and division operations.
(d) Multiplication and division operations are skipped over if the corresponding factors and dividends are zeros. This feature together with the feature of unnormalized significant digit arithmetic reduces the time for scientific computations quite remarkably
(e) All arithmetic and transfer operations are performed under pre-set length condition. This feature enables the programmer to pre-set the maximum length of numbers for a given set of data, within which an individual number may gain or lose significant digits. If, as a result of addition or subtraction, a number gains a significant digit beyond the present length, then (i) in the case of significant digit operations, the number is right shifted one character and the exponent adjusted automatically; (ii) in the case of generalised fixed point operations, an automatic interruption of the programme occurs. The interruption also occurs whenever a number arbitrarily longer than the pre-set length tries to take part in arithmetic or transfer operations. This novel feature automatically protects information stored in the memory from being accidentally destroyed by the variability of word-lengths and thus relieves the programmer of the burden of scanning the length of each number before storing it in the memory. Normally, the maximum for which the pre-set length facility is available in 31 characters, but this can be inhibited by programmes, and one can operate on numbers as long as one desires.
(f) The fully time-shared, autonomous operation of all peripheral equipment is a very important feature of the machine. This feature will be particularly useful in the transfer operations involving the magnetic drum, tape or disc, enabling the computer to approach the speed of core memory although using two-level memory. Consistent with this feature, there is also the facility for the interrogation of the channels as to their conditions.
(g) The machine has also the important facility for automatic interruption of programmes for both internal and external reasons. The internal interuptions occur for conditions like over-flow, division by zero, violation of pre-set length condition, etc. The external interruption occurs because of operator intervention through the Console Typewriter during programme run.
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6. Speeds of operations:
The operands are assumed to have six-character mantissa and one-character exponents for the following estimate of calculation time. (A six-character binary number is equivalent to 11 decimal digits).
(1) Addition Subtraction ?????????????????????????????????????? ?--- less than ???100 μs
(2) Multiplication ????????????????????????????????????????????????????--- less than ???700 μs
(3) Division ????????????????????????????????????????????????????????????--- less than ???900 μs
(4) Address arithmetic ???????????????????????????????????????????--- less than ?????24 μs
(5) Jump unconditional ????????????????????????????????????? ????--- less than ?????10 μs
(6) Instruction Fetch time:
(a) For unmodified direct single-address????? ?--- less than ?????32 μs
(b) For modified direct single-addons???????? ??--- less than ?????56 μs
(e) For modified indirect single-address ??? ???--- less than ?????80 μs
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The solution of a set of linear equations involving 40 unknown parameters will take less than 1 minute 15 seconds and that for 20 unknown parameters will take less than 10 seconds on the machine.
V. Comparison of ISIJU with the other contemporary machines?
In this section, an attempt is made to compare ISIJU architecture and performance with a few contemporary machines. The comparison is mostly qualitative because of the unavailability of detailed Instruction Set Architecture (ISA) and the quantitative data regarding the other machines. Even for ISIJU, the quantitative information available was not very detailed.
Performance Figures for Atlas [6]
Note: Blanks indicate figures could not be found.
Benchmark figures of Atlas
"In 1967 a benchmarking comparison for 22 compute-bound Fortran scientific jobs was performed on an Atlas with 32k core, a single-processor Univac 1108 with 64k core, and a CDC 6600 with 64k core. The compilers used were respectively the London non optimizing Atlas Fortran V, the Univac F4012 Fortran IV, and the CDC Chippewa Run. Under these conditions the average CP computing speeds for Atlas, Univac 1108, and CDC 6600 were measured to be in the ratio 1: 2.1: 5.9 respectively."?
[Ref. Manchester Mark I and Atlas]
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Benchmark figures of ISIJU-1
Solution of a set of Linear equations with 20 unknown parameters took 10 secs. and with 40 unknown parameters took 1 min. 15 secs. in ISIJU. [Ref. Report published by ISI and JU Joint Computer Project Committee on the occasion of the inauguration of Computer ISIJU-1]
IBM 1401 [7]
IBM 1620 [8]
IBM 1130
VI. ISIJU Circuits & Components
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1. INTRODUCTION
ISIJU used Diode-transistor logic (DTL) circuitry [1] for the logic operations. The Diode used for logic operation was 1N276 by Transitron of Boston, MA. For the control memory of the micro- programed control unit, 1N270 diodes by Transitron were used. The 1N270 was faster than 1N276.
The transistors used were of two types: (a) 2N404 [2,3] from RCA of New Jersey and (b) 2N1499A from Sprague Electric of Massachusetts. Please see the pictures below.
The picture below shows a basic PNP Transistor Configuration. VBE = 0.3 Volt for Germanium Transistors and 0.6 Volt for Silicon Transistors. ISIJU used only Germanium Transistors. VCE = around 0 Volt when the transistor saturates. In DTL logic, the transistor is off for one logic level and saturated for the other logic level.
2. ISIJU LOGIC CIRCUITS
2.1 Logic Circuits
In ISIJU, the logic "0" was represented by 0 volt while logic "1" was represented by -6 volt. As pointed out earlier, ISIJU used DTL logic which is illustrated below.
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The DTL circuit shown in the picture above consists of three stages: an input diode logic stage (D1, D2 and R1), an intermediate level shifting stage (R3 and R4), and an output common- emitter amplifier stage (Q1 and R2). If either of inputs A and B are high (logic 1; near V-), then the diodes D1 and/or D2 will be forward biased and will then supply enough current to turn on Q1 (drive Q1 into saturation) and supply the current needed by R4. There will be a small positive voltage on the base of Q1 (VBE, about 0.3 V for germanium and 0.6 V for silicon). The turned-on transistor's collector current will then pull the output Q low (logic 0; VCE(sat), usually less than 1 volt).
The DTL propagation delay is relatively large. When the transistor goes into saturation from all inputs being high, charge is stored in the base region. When it comes out of saturation (one input goes low) this charge has to be removed and will dominate the propagation time.?
One way to speed up DTL is to add a small "speed-up" capacitor across R3. The capacitor helps to turn off the transistor by removing the stored base charge; the capacitor also helps to turn on the transistor by increasing the initial base drive. In ISIJU implementation, this speedup capacitor approach was used extensively at the input of the transistors. The circuits in this section do not show the speedup capacitors but it should be assumed that they have been used.
If both inputs are low (0 volt) in figure above, then input to the R3 will be around +0.6 volt. R3 and R4 then act as a voltage divider that makes Q1's base voltage positive and consequently turns off Q1. Q1's collector current will be essentially zero, so R2 will pull the output voltage Q high (logic 1; near V-).
In order to ensure that there is a well-defined logic 1 (-V volt) at the collector of the transistor Q1 when it is off, in ISIJU a "clamping" scheme was used as shown below.
In ISIJU, V+ Voltages were either +6 Volt or +20 volt and V- was -20 Volt. The clamping voltage VC-was-6 volt so that with a diode drop of around +0.6 volt, the collector voltage when Q1 was off got clamped at -6 volt defining the logic 1 correctly. The D1, D2 combination formed an OR gate while R3, R4, Q1, and R2 formed an Inverter. Logically, if Q1 output is labelled C, the circuit above implements the following logic:
Similarly, the circuit below is a combination of AND function and Inverter. This circuit implements the following logic:
In ISIJU, the AND function, and AND functions and the Inverter functions were segregated in different packages.
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2.2 Emitter Followers
In addition to AND, OR, and Inverter functions, the ISIJU also used Emitter Followers anywhere it needed to provide high powered drive capability after the output of either AND or OR functions.
The circuit below shows the implementation of the Emitter Follower function.
In the picture above, D1, D2, and R1 combination implements an AND function while R2, R3, R4, Q1, and D3 combination implements the Emitter follower function. Logically, the output C is still the AND of inputs A and B but at the output C, the drive capability is a lot higher. This is a very "clever" circuit arrangement as the output C can source and sink substantial amount of current at both logic 0 (0 volt) and logic 1 (-6 volt) level.
For instance, when C is at logic 0 level, the diode D3 can sink more than 50 ma as D3 is implemented using 1N276 which can sink lot of current. At logic 0 level, the +V volt supplies current to the outside circuit through R4 and the amount of current it can source is dependent on R4 value.
At logic 1 level, the -6.5volt at the collector of Q1 sinks the required load current and V+ supply through register R4 can source almost unlimited amount of current.
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Complementary Emitter Follower
In addition to the Emitter follower, for driving long cables (e.g., inter-connecting CPU with Tape Reader for example, complementary Emitter Followers were also used).
The configuration below shows the complementary Emitter Follower Circuit design used in ISIJU.
2.3 Flip-Flops
ISIJU used two different types of Flip-Flops: (a) S-R (Set -Reset) and (b) T-Flip Flop (Toggle). A flip-flop is a term referring to an electronic circuit (a bistable multivibrator) that has two stable states and thereby is capable of serving as one bit of memory.
The truth tables below describe how the outputs of a given flip flop will be determined by a combination of inputs. Not shown are Preset and Clear inputs, which will cause the "Q" outputs to be set high or low, respectively.
?The picture below shows the configuration of a typical Flip-Flop used in ISIJU. The inputs of the figure below in ISIJU Flip-Flops have typically an OR Gate (2 input).
Most of the registers in ISIJU were constructed out of banks of SR Flip Flops and the Counters were constructed using bank of T- Flip Flops. ISIJU logic circuit design was basically Asynchronous. Except for the CPU, the other circuits did not use a time pulse from the central clock. The clamping circuitry using a diode terminating at -6.5v is not shown in the diagram.
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2.4 Monostable Multivibrators
In the design of the memory control systems and the peripherals like Tape Reader and Tape Punch, chain of Monostable Multivibrators was used to create timing pulses for different functions.
The function description of a Monostable Multivibrator is shown below. This circuit has one stable state, and a triggered pulse provides enough energy to move it from a stable state to another stable state for certain period determined by the values of R & C below. The typical pulse length created by Monostable Multivibrators in ISIJU was around 1 μsecond and the longest pulse length was a few milliseconds used in peripherals.
2.5 Astable multivibrator
Astable multivibrator is a configuration in which the circuit is not stable in either state-it continually switches from one state to the other. It functions as a relaxation oscillator.
The circuit above shows the configuration of Astable multivibrator using PNP transistors. ISIJU used only one such circuit as a clock in the micro-programmed control unit. This clock drove the control store to create 142 basic P-Pulses and each P-Pulse was used to execute 1 micro instruction for a particular instruction. The oscillation frequency formula is as follows:
If R1 =R2 =R and C1=C2=C, the oscillation frequency is:
The clamping circuitry using a diode terminating at -6.5v is not shown in the diagram above.
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2.6 Packaging
Each package was implemented using a Vero Board as shown below.
The Vero boards plug into individual connectors. The edge fingers above were gold plated for good conduction and made positive contact with connector pins. A Vero/edge connector is shown below.
A typical package would have (a) multiple AND or OR functions (2-input, 4-input, or 8-input), (b) a number of Inverter circuitries, (c) two Flip-Flops, (d) two Emitter Followers, etc.
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VII. Conclusion
?In the annals of the evolution of computers over the last 80 years, ISIJU and its history most probably are mere blips but for India and especially West Bengal, ISIJU's history has special significance.
Prof. Prasanta Chandra Mahalanobis of ISI was one of the very few persons in India to recognize the importance of computer technology. In 1950 he planned to purchase Hollerith Computer. In August 1950, he met IBM President Watson Sr. and talked about the MARK-I automatic high- speed calculator. A small electronic digital computer called HEC-2M (Hollerith Electronic Digital Computer-2M) produced by the British Tabulating Machines Works, Letchworth had been ordered in 1954. Monimohan Mookerji and Amaresh Roy completed their training in the British Tabulating Machines Works at Letchworth and visited different computing machine laboratories in Europe and returned to India early in 1956. The HEC-2M was received in February 1956 and installed by them in about a month in an AC room situated on the ground floor of the Institute building and it was ready for operation by the end of March 1956. This was the first electronic computer to be installed in India and the Indian Statistical Institute was the first to turn out trained programmers. During 1955 the USSR Government had offered the Institute a big electronic digital computer called URAL through the UNTAA (United Nations Technical Aid Administration). Samarendra Kumar Mitra and D. S. Kamat were deputed to the USSR in September 1955 by the UNTAA on a special fellowship, to make a technical report on URAL. They visited Moscow, Penza and other places and gathered experiences concerned with computing machinery [13].
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The URAL computer was received in March 1958 and installed on 20 December 1958 in the institute for processing of statistical data by the Soviet engineers who handed it over to the Institute for use in February 1959. Mr. Touri Diatlov, Mr. Dimitri Loohtehinine, Mr. Alexandre Loginov, Mr. Boris Komarov, Mr. Ashraf Akhmed Zianov were in that team [13].
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The design and implementation of ISIJU was in one sense the continuation of pioneering efforts by Indian Statistical Institute (ISI) in Calcutta in the computer field.
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The successful inauguration of ISIJU-I created a lot of interest among the students as well as the members of the public in computers as an academic discipline. Many aspiring students expressed their interest in studying different aspects of computers and this resulted in Jadavpur University (JU) approaching the University Grants Commission (UGC) to start a separate academic program in Computer Science.
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UGC readily agreed to the proposal and created a Computer Centre by sanctioning adequate funds for personnel, building, equipment, books, research fellowships, etc. This culminated in the ETCE Department starting a Postgraduate (PG) Diploma program in Computer Science in 1968 having two streams - Hardware and Software - with a total intake of 20 students from all over India. The software stream was open to engineering graduates of all disciplines as well as candidates who completed M. Sc. in Physics or Mathematics.?
This PG program, one of the earliest in the country, was extremely popular and ran very successfully till 1982, when the 1-year diploma program was converted to a 2-year degree program, Master of Computer Science and Engineering (MCSE), with additional grant from UGC. The MCSE program started with an intake of 30-15 from West Bengal and 15 from other states. Earlier a 4-year Bachelor of Computer Science and Engineering (BCSE) program was started in the ETCE department in 1981 with an intake of 30 – 15 from West Bengal and 15 from other states of the eastern region.
After ISIJU was completed, because of pioneering efforts of Prof. Biswajit Nag, the Government of India decided to set up a number of Regional Computer Centers (RCC) in different parts of India. The first one was set up in Jadavpur University Campus in Calcutta in 1976 and was ultimately merged in 2002 with DOEACC Society - An Autonomous Scientific Society of Department of Electronics & Information Technology under Ministry of Communications & Information Technology, Govt. of India [9].
The Regional Computer Centre at Jadavpur installed a B6700 system manufactured by Burroughs Corporation, USA, as its central computer resource. Burroughs 6700 was part of a family of large 48-bit mainframes using a stack architecture. It used monolithic integrated circuits with magnetic thin-film memory. The cycle time of memory was 0.5 μsec/1.2 μsec/1.5 μsec depending on the model. This machine, introduced in 1971, was optimized for ALGOL 60 using a single-pass compiler. The entire hardware was designed to support high-level programming languages such as ALGOL, FORTRAN, COBOL, PL/1 and BASIC. It also had support for symmetric multiprocessing. In addition to the implementation of virtual memory it also supported the segmented memory model. The machine was widely acclaimed as a system well ahead of its time.?
The architecture was designed to support virtualization of memory and multiprocessing. Special 3-bit tags were attached to each word of memory (in addition to the basic 48-bit word) to restrict the ways that word could be used. Because there was no user access to machine language it was possible to relocate programs and data in real memory without having need for a page-table mapping.
The trick to speed up the system was to keep data as close to the processor as possible. This was done by assigning the top two positions of the stack to two registers A and B. Most operations are performed on these two top-of-stack positions. On faster models, more of the stack was kept in registers or cache near the processor. This enabled the programmers not to recompile or alter their codes in any manner while elevating them to a higher model to achieve significant speed advantages, thereby saving significantly on software investment. [14]
The Burroughs B6738 system was installed at RCC in 1977. Being the first multiprogramming facility in the eastern region of the country, this machine could cater to a large number of academic and industrial users. Many new applications such as Large-scale simulation and Optimization-oriented packages were developed on this machine during this time. The usage grew so much that the Centre soon had to give service round the clock. User organizations, happy with the services they received, obtained special purpose packages from abroad and donated them to the Centre for everybody's benefit.?
A Remote Terminal of the system was installed at Mecon, Ranchi. The then poor communication infrastructure could provide reliable communication between the mainframe and the remote terminal at best up to 300 bps. Even then, the experimentation was important as users could gain access to the system in real-time bypassing the usual route of submitting punched card decks and obtaining line printer outputs after several hours.
Clearly, these regional computer centers provided easier access to computing resources to researchers and students in different parts of India and this access was instrumental in training a large cadre of engineers for careers in the IT industry.?
The other significant event was the decision by Tata Electric company to set up a subsidiary called Tata Consultancy Service (TCS) in late 60's [10]. This was a pioneering decision.?
In 1973, TCS partnered with Burroughs to distribute and support its products in India as well as to build software that would be exported to various Burroughs units and clients across the world. TCS converted a hospital accounting system written in Burroughs Medium Systems COBOL to Burroughs Small Systems COBOL. At this point, TCS did not yet have a Burroughs computer on which to carry out the conversion. The team improvised by writing a 'filter' in assembly language on the ICL 1903 to parse the source code and convert it to the Small Systems version. This was the very first recorded instance of an offshore software delivery done out of India, 45 years ago, accomplished using automation [11].?
The IT industry in India accounted for 8% of India's GDP in 2020. Exports from the Indian IT industry are expected to increase by 1.9% to reach US$ 150 billion in FY21. In 2020, the IT industry recorded 138,000 new hires. The IT & BPM industry's revenue is estimated at ~US$ 194 billion in FY21, an increase of 2.3% YoY [12].
This phenomenal achievement by India's IT Industry has its genesis in efforts by ISI and Jadavpur University engineers in Calcutta as well as the pioneering efforts of the visionary founders of TCS.
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VIII. Acknowledgement
This history of the ISIJU project has been compiled by Dr. Lakshmi N. Goyal, Dr. Santanu Das and Dr. Pradip K Das.
The section VI was put together by Dr. Santanu Das based on his recollections. Any inaccuracy or omission is due to not having access to ISIJU design documentation.?
Santanu Das and Pradip das would like to thank Dr Lakshmi Narayan Goyal, their collaborator, for painstakingly copying his ME thesis [15] and the Souvenir [16] published at the time of commissioning ISIJU-1.
The authors thank their colleagues in the ISIJU project for their pioneering efforts against heavy odds - especially the lack of adequate funding. Hopefully, this compendium will do justice to their contribution.
Ms. Shafali Sharma, Digital Marketing Analyst at DomaniSystems Inc. in Connecticut, USA, deserves special thanks for putting this document together. Without her efforts, this compendium could not have been produced.
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IX. References?
1. Diode-transistor logic https://en.wikipedia.org/wiki/Diode%E2%80%93transistor_logic ?
2. PNP Transistor https://www.electronics-tutorials.ws/transistor/tran_3.html
3. RCA - 2N404 - Transistor, PNP. P/N: 2N404 https://www.electronicsurplus.com/rca-2n404-transistor-pnp-p-n-2n404
5. Vero/edge connector https://uk.farnell.com/amp-te-connectivity/2-5530843-7/card-edge-conn-dual-side-36pos/dp/2452380
7. IBM 1401 https://en.wikipedia.org/wiki/IBM_1401 ?
8. IBM 1620 https://en.wikipedia.org/wiki/IBM_1620 ?
9. NIELIT https://www.nielit.gov.in/content/introduction-12
10. FC Kohli https://science.thewire.in/the-sciences/f-c-kohli-india-information-technology-industry-ibm-tcs-burroughs/
11. TCS https://www.tcs.com/tcs-50 ?
12. Indian IT industry size https://www.ibef.org/industry/information-technology-
india.aspx#:~:text=The%20IT%20industry%20accounted%20for,industry%20recorded%20138%2C000%20new%20hires.&text=The%20IT%20%26%20BPM%20industry's%20revenue,an%20increase%20of%202.3%25%20YoY??
15. Lakshmi Narayan Goyal, "Logic Design of Control and Arithmetic Units of a Character- Organised Digital Computer with Special Reference to Multiplication Function", M.E. thesis, Jadavpur University
16. Souvenir on the occasion of Commissioning of the Digital Computer ISIJU-I, Jadavpur University, 1966
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X. Appendix?
Biographies of Key Members of ISIJU Project?
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A brief biography of Prof. J.S. Chatterjee
Prof. J.S. Chatterjee did his D. Phil under the supervision of Prof. S.K. Mitra and started his teaching carrier at the department of Radio Physics in the University of Calcutta. Thereafter he joined the College of Engineering and Technology founded by the National Council of Education, Bengal at the behest of Dr. Triguna Sen in the year 1955. He took charge of Communication section of the department of Electrical Engineering. The College of Engineering and Technology became Jadavpur University in 1956 and Prof. Chatterjee became the founder of the Department of Telecommunication Engineering in 1957.
Before joining College of Engineering and Technology, Prof. Chatterjee earned recognition, name and fame because of his pioneering research on broadband and frequency independent antennas at the Science College of Calcutta University. As a founder Head of the Department of Telecommunication Engineering of Jadavpur University he was tremendously successful. He continued his research work on broadband antennas and guided a number of Ph.D students. The department also expanded at very rapid rate with Computer Science and Engineering. Electronics and Instrumentation Engineering as separate individual specializations. By that time the department of Telecommunication Engineering got renamed as department of Electronics and Telecommunication Engineering. Finally all branches of the department flourished so much that after his retirement the original department got trifurcated amongst the departments of ETCE, CSE and IEE. Each of the three departments have quired high credentials among the academic community of the world by this time.
He had great patriotic contribution in nation building too. He undertook a tremendously courageous step to establish a clandestine radio station called "Swadhin Bangla Betar Kendra" during the liberation war of Bangladesh in 1971 at his own departmental premises.
Under Prof. Chatterjee the first operational digital computer in India called ISIJU-I was fabricated and installed at Jadavpur University as a joint venture with ISI. He was invited by NASA for carrying out research work on antennas related to Satellite Communication especially conical helix. He had been acclaimed greatly there for his contributions. He also served as visiting professor and researcher at various countries abroad.
Prof. Samarendra Kumar Mitra
With the age of computers invading our modern lives almost in every space, one Bengali scientist's name is often forgotten to be mentioned as the one who made India's first computer! Yes, he was not only a Bengali mathematician from Indian Statistical Institute (ISI) of Kolkata, but also the founder and first head of the Computing Machines and Electronics Division of ISI. Samarendra Kumar Mitra is almost forgotten as a pioneer in India's scientific progress, yet it is he who designed, developed and constructed in 1953, India's first indigenous electronic analogue computer for solving linear equations with 10 variables and related problems.
This computer was used in computation of numerical solutions of simultaneous linear equations using a modified version of Gauss-Seidel iteration. Mitra is indeed the ‘Father of Computers in India' and his work and biography can be found in the History Museum of Computers in California. Subsequently, in 1983, the ISI started the design and development of the first second-generation indigenous digital computer of India in collaboration with Jadavpur University. This collaboration was also led by Mitra, as he was the Head of the Computing Machines and Electronics Laboratory, ISI. He designed, developed, and constructed a general purpose High Speed Electronic Digital Computer, namely ISIJU computer. Under the leadership of Mitra, the first second-generation ?indigenous digital computer of India was thus produced, namely the transistor-driven machine ISIJU-1, which became operational in 1984.
Prof. Biswajit Nag
Prof. Biswajit Nag was the Director of Indian Institute of Technology, Bombay from September 1984 for ten years. During his tenure as Director, Prof. Nag played a major role in restructuring of academic programmes, modernization and obtaining substantial Government and Industry support for the institute. Earlier from 1978 to May 1981 he was appointed as the Chairman, Electronics Commission and Secretary to the Department of Electronics, Government of India at New Delhi. He has been a pioneering educationist to establish Computer Science and Engineering studies in the Indian Universities and the IIT. Prof. Nag was recipient of many awards and honours including the S.K. Mitra Memorial Award. He was also associated with several scientific, professional and industrial bodies and organizations in the country like Fellow, Indian Academy of Sciences, founder member and Fellow, Computer Society of India. Since September 1994, he was a Consultant to Electronics, Computer and Telecommunication Industries and Financial Institutions.
Dr. Biswajit Nag earlier had joined as a lecturer in the ETCE department, JU after obtaining his M.Tech in Radio Physics and Electronics from Calcutta University in 1955. Prior to this, Dr. Nag had a brief stint at ISI where he worked under Prof. Samar Mitra. Dr. Nag also worked as a Research Scholar at Manchester University under the Commonwealth scholarship. There he worked on Atlas Computer - one of the world's first supercomputers.
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Prof. Asish Sen
Prof Asish Sen joined Indian Statistical Institute in the Electronics Unit after completing his BSc- MTech in Radio Physics from the Rajabazar Science College in 1957. He was part of the team operating the HEC-2M, the first electronic digital computer to be installed in India. One of his landmark contributions to the nascent computing environment in India in the 1960's was the first solid-state electronic computer developed indigenously as part of collaboration between ISI and Jadavpur University-code-named ISIJU computer. This was in 1965.?
Prof Sen continued to be a member of the Electronics Unit and Physical and Earth Sciences division of ISI, where he worked in various capacities such as Professor, Professor-in-charge. In 1986, he took a sabbatical from ISI and joined Webel to further the development of IT/Electronics industry in West Bengal. As Executive Director Special Projects for West Bengal Electronic Communication System (WECS), he led many successful R&D and Telecom projects such as the 100k lines Automatic Message Accounting (AMA) Systems for Electromechanical Exchanges of Mahanagar Telephone Nigam Limited (MTNL), Mumbai during 1990-91 – the project received Award of Excellence (First Prize) by the Department of IT (erstwhile Department of Electronics), Government of India in the year 1990. Some of the projects that received huge recognition was development of software for scanning "new Voter id card" and communication system set-up at the second Hooghly bridge toll booth.
Later he joined the Executive leadership team of WEBEL as the Executive Director (Technical) and played a very important role in the development and expansion of various industries at Sector V, Salt Lake between 1991-2000. He had served as Executive Board Member of many companies, a Health institute and also served as President of one of the Govt Institutes in West Bengal.
He retired from ISI in 1993.
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Dr. Ambarish Ghosh
1. Born: 1932, Calcutta
2. Academic Record:
a. 1951: 1st class 1st- B.Sc. Honours in Mathematics, Calcutta University
b. 1953: 1st class 1st - M.Sc. in Applied Math, Calcutta University
c. 1955: Joined ISI (Indian Statistical Institute), Calcutta as a programmer of HE2M, Electronic Computer (The first electronic computer in India)
d. 1956: Went to France with a French Govt. Scholarship, for higher studies.
e. 1958: Ph.D. in Mathematics from Univ. of Aix-Marseille, France
f. 1960: D.Sc. in Mathematics from Univ. of Aix-Marseille, France
g. 1960: On return from France, joined ISI, Calcutta
h. 1963: Went to USA, with United Nations Fellowship, joined Institute for Computer Research-Chicago University.
i. 1964: On return from USA, joined ISI, Calcutta and took part in the ISIJU Project for the fabrication of Fully Transistorised Electronic Computer with Prof. E. V. Krishnamurthy. Sri Prabhat Kumar Mitra prepared the logical design of the ISIJU Computer, which was inaugurated in 1966.
3. Teaching Experience:
a. 1964-1995: Taught Fluid Mechanics at the Dept. of Applied Math of Calcutta University as a guest Professor.
b. Taught Logical Design of Computers and Numerical Analysis to the students of ISI.
c. 1992: Retired from ISI at the age of 60.
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Dr. E. V. Krishnamurthy
Dr. Krishnamurthy was a lifelong member of ISI staff. He was one of the architects of the ISIJU-1 computer.
He was a professor at the Department of Computer science, Indian Institute of Science, Bangalore. He was an Emeritus Fellow, Computer Sciences Laboratory, Research School of Information Sciences and Engineering, Australian National University, Canberra.?
He received the prestigious Shanti Swarup Bhatnagar Award for Science and Technology (1978). He held several positions working for many institutions in India, Australia, USA, Europe and other nations. He expired in Canberra, Australia, in 2012.
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Rewritten, edited & posted by: Debasis Bera
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