High speed electronic devices challenges

Designing high-speed electronic products brings many challenges. High-speed busses such as PCI-Express, DDR3, and Serial ATA run at frequencies from several hundred megahertz to more than a gigahertz, making for tight timing margins. Fine-geometry silicon generates fast edge rates. And growing pressure for smaller and cheaper products leads to very dense PCB layouts. To implement a successful high-speed PCB design, all these factors must be taken into consideration.

?There are three main areas of concern when creating electronic products with high-speed design constraints:signal quality, timing, and crosstalk.

?Signal quality includes items like overshoot, ringback, and non-monotonicities that can damage a receiver or introduce data errors.

Timing, including effects of terminations, receiver loading, and trace impedances and lengths, must be rigorously analyzed at the PCB level to ensure compliance at the system level.

Crosstalk, which is unwanted noise induced by one trace onto another, can affect both signal quality and timing.

?By analyzing these areas you can improve product reliability and quality by testing what-if scenarios, generating routing constraints, and validating them in layout to ensure your electrical requirements are met. Through analysis, you can also drive sensible decisions about trace lengths, topology, spacing, and part placement, and constrainitems such as board stackup, trace widths, and copper weights.

?SIGNAL QUALITY

?Digital logic reduces data to a series of 1s and 0s, which are represented in a real system by high and low voltages.In order for a receiver to determine whether or not a voltage represents a 1 or a 0 that voltage must be above orbelow the logic thresholds of the receiver. Also, that voltage must not exceed the limits of the receiver or it mightbe damaged. These two requirements generate two fundamental constraints in signal quality analysis: ringbackand overshoot.

If a designer or engineer were to just connect a transmitter to a receiver, the result would be something like thewaveform shown in Figure 1 on the left side. Here, we can see there are both ringback and overshoot violations.The waveform shows negative overshoot in excess of 1V. It also rings back to 0.8V, which is the lower logicthreshold. If a PCB were built with this topology as is, errors in the data stream would occur and the receivers couldbe damaged.

If the length of the topology is reduced significantly, to well below the length of our signal edges, the receiverwaveform is cleaned up dramatically. This can be seen in Figure 1 on the right side. Unfortunately, however, suchlengths are typically on the order of an inch or so, which is not always feasible in a design.

Another method of cleaning up the signal at the receiver is to use termination to match the impedance of the drivers and receivers to the board traces. This lets you control the reflections that create overshoot and ringbackviolations. Termination also allows for greater flexibility in topology length as trace lengths aren’t restricted to anunrealistic maximum and cleaner signals can be obtained.

?TIMING

?Most length constraints in a design are driven from a timing need. Timing needs come from the fact that data is “clocked in” to a receiver at certain intervals. If the data are not there when the system needs them to be, the system doesn’t work.

?There are two main types of bus timing architectures: common clock and source synchronous. These lead to two types of layout constraints: min/max and matched lengths. Minimum and maximum delay constraints are createdfrom common clock bus architectures.

?An example of this is PCI, where data are clocked out of a transmitter and into a receiver using a common clock. Inorder to make sure the data are not there too early, or violate the hold-time requirement, a minimum lengthconstraint must be created. Similarly, to ensure that data do not arrive too late, a maximum length constraint iscreated. These constraints are not based merely upon the length of the line. Many other considerations, such asreceiver loading and signal quality issues, determine when the transmitted data may be valid at the receiver, soproper signal analysis is critical for calculating these lengths appropriately.

?Matched delay constraints come about from source-synchronous busses. These busses, such as DDRx, send aclocking signal or “strobe” along with the data in order to ‘clock it in’ at the receiver. This eliminates the complextiming relationship between driver and receiver, and requires only the matching of the strobe to the data. Typically,these interfaces have other concerns, such as signal quality, which determine when the data are valid. The maintiming constraint for these busses is the matched delay constraint, which becomes tighter with increases in busspeed or signal quality problems.

?CROSSTALK

?

Another important constraint for the layout of the design is the spacing between traces. This is determined by the amount of crosstalk that occurs between the signals. A number of factors influence crosstalk, including: the edgerate of the driver, the board stackup, the amount of parallelism between traces, and the spacing between traces.Crosstalk affects both signal quality and timing, and the amount of crosstalk allowed on a given net can bedetermined from simulation.

?Crosstalk analysis typically consists of a “victim” trace and two “aggressor” traces. More aggressors can be includedbut, in most ases, 95% of the crosstalk comes from the nearest two. With models for the driver, the receiver, andthe board stackup built into the simulation, you can modify the spacing between the traces to determine anacceptable level of crosstalk. You can also modify the length that the traces run parallel and view the effects. Themain result of such an analysis is a spacing rule between traces. If that spacing rule cannot be met, or if greaterflexibility is to be allowed in the layout, a rule could be created with tighter spacing and a maximum parallelism constraint. Such a pair of constraints can be created from crosstalk analysis and modified as demands change.