HDL code Linting first review test

with what i need to start ? this is main question, let me put my opinion about it, means about linting. It is a process to find the potential error, like logical errors, syntax error. And if we know the errors, we try to correct it by our own to produce the quality RTL. And again I want to add into this> quality RTL does not mean desired functionality, in my view it is logically error free now not more than that. Who knows ! code desired functionality which is designed by you is really required[quality] functionality of module.

Anyway logical errors like [1 div by zero [2 width mismatch [3 constant conditions etc. can be find by such tools process, i mean linting process.

lets start with it, one more who need this tool ? beginners, freshers, and experiences designers peoples, i mean experiences people who has beginners, freshers as team members. i hope you got this. sorry to say [beginners, freshers]

It not means that experiences design people dont not need it, as these are experiences people so they have lot to do! there code size is large, not always possible to look forward to each and every things, then this tool process give a hand to these peoples, come on BRO !, i will take care of it, don't worry. this is what i think, may be others have there own way to think.

let start with it, on a start of tool[sypglass], you get the flash screen which is show at top of this article and then the screen comes as below.

I am referring the content from link https://mslab.hanyang.ac.kr/IDEC_VERILOG_day2.pdf for test the process. One more[it is spontaneous, it comes into mind i just add it ] i need to add as it is error finding tool so for that i need to add errors into the code to test it, which is very hard for me, because number of years i spends to write code which is error free. so i prefer to link document for the same which give some relief.

For better start i first go with error free code, which is just full adder, 2 half adder + or gate

The tool flow is very simple, go to file make new project, give name, location, after that a screen change, shows list of folders, by clicking the add design files, you are able to add source files that's it. it is similar to all other tools [ new project, add files] ok. After adding files. Click on design setup, it ask for synthesis netlist, etc. i just check mark that[ which will generate the schematic as well] and read the design and elaborate. after the process you will get the summary in the bottom of window which is show in above snap, all msgs are in green color means there is no severity error in reading and elaborating the source in first stage.After clicking the MS[and gate button] you will get the schematic window just like below.

>> here i took 4-5 ex with first code is bism1[badimplicitSM1] , obviously it has error

from the code it is clear also, when it comes to lint tool it gives error as Identifies the Un-synthesizable modelling style for sequential logic, where clock and reset cannot be inferred - Unsynthesizable - Severity level: Error

same error with zoom, with expand list of msg. To check the design there are numbers of goal rules. What i tell upto now it is for linting in basic way, but some tools like spyGlass also provide the linting for cdc, dft, power etc which is listed in bottom snap, which is very good to know. now it is not just logical error finding tool it is also a checker for following lists of items. [note there are lots more items in the list, cant fit in please ref the other doc for the same]

linting people called these are goal rules/linting rules/ methodology for the same.

>>Ex2 ,bism2 code has error

Identifies the implicit sequential logic in a non-synthesizable modeling style where states are not updated on the same clock phase - The synthesis tool can get confused about which edge to use for updating the register - RTL and gate-level simulation results may not match.- Severity level: Error

>> EX3 bism4 code, it has error as well as seen from code itself.

- Identifies the non-synthesizable implicit sequential logic where event control expressions have multiple edges - The synthesis tool can get confused about which edge to use for updating the register - RTL and gate-level simulation results may not match - Severity level: Error

>>Ex4 code bothedge.v also has error, i mean i put it for you.- Identifies the variable whose both the edges are used in an event control list - Synthesis tools do not allow both edges of the same variable in an event control list - Severity level: Error

>> Ex5 code mixedsense.v also seen error , and it detected as above. - Mixed conditions in sensitivity list may not be synthesizable - It flags mixed edge and non-edge conditions in the sensitivity list of an always construct. - Severity level: Error

Do comment for any more examples or any such tool explanations. i want to declare that its my own opinion[whatever seen above] about the lint process and the tool. Please do ref other resources for more detail as it is just a slice of lint process. that's it, Okay!