Hardware Description Languages and Verilog (Combinational Logic) - GCA 002

HDL or Hardware Description Language has always had an aura of impossibility or at least immense difficulty to it. Even though creating logic on Model Electronic Systems is an older science compared to Software Development and is more fleshed out and yet Software Engineering has still managed to be the easiest beginner friendly because of the amount of documentation that exists for people just entering the industry.

This small write up is addressed to how handle with getting started with HDLs and how to get over the barrier of learning. HDL follows the Dunning-Kruger Effect passionately, and as much as it is exciting to get down these difficult logics, do approach it with a humble mind set.

Approach to Deal with complexity

As mentioned before, there is no walking away from the fact that micro-architecture is a difficult vocation, it is not served up with the most easy to get into accessibility.

Below is Intel's 2017's Kaby Lake

With its 64- bit processor , it's 4 cores and 8 threads , it's amazing 14-19 stage pipeline, 3.9 GHz clock, it's 1750000000 transistors.

Now that's a lot of jargon and a lot of number of things, and in around 47 years, about 1,000,000-fold growth in transistor count and performance has happened.

And one of the easiest way for humans to work with these amazing counts and arrangement of transistors and getting them to work to their fullest potential are the Hardware Description Languages.

With any language from Python to Verilog , there are certain criteria they have to fulfill which are a fact of life in computer engineering :

• They need to be able to Specify complex designs - to communicate with others in your design group
• And they must be able to Simulate their behavior - So that it's clear what one want to build
• And to Synthesize (automatically design) portions of it - to have an error-free path to implementation

And thus Hardware Description languages are built in accordance to solve such problems

Many similarly features HDls are Veriglo , VHDL and so on. To make sure that the new languages are still relevant, most of the HDLs are very similar in syntax and other sense. So if you learn one, it is not hard to learn another, and this is very important to keep in mind!

Mapping between languages is typically mechanical, espcially for the commonly used subset.

Popular and well-known, top dogs of HDL

Verilog

• Developed in 1984 by Gateway Design Automation
• Became an IEEE Standard (1364) in 1995
• More popular in US

VHDL (VHSIC Hardware Description Language)

• Developed in 1981 by the US Department of Defense
• Became an IEEE Standard (1076) in 1987
• More popular in Europe

We would be focusing on Verilog from GCA 003 and diving into it's hierarchical design.