Hands on Sigma Delta modulators part 3

Please start with parts 1 and 2...

Sorry, now is the time for some (simple) calculations. First, we need a small signal equivalent schematic:

Input difference and integrator achieve a transfer function H1(s) = 1 / (T*s) where T is the integrator time constant. H1 has no dimension, translating a voltage into another voltage.

Even if not obvious at first sight, Comparator+DFF achieve a small signal gain H2 = K. H2 has dimension 1/Volts, translating volts into a digital value that has no dimension. K value is a bit tricky and will be detailed at the end of this post. For now, let's admit small signal K exists.

Feedback DAC achieves small signal gain A. A has dimension Volts, translating no dimension into volts.

This model is sufficient to calculate closed loop gain. It can also be used to calculate signal at integrator output. Equations write:

V(int) = (V(in) - V(fb)) / (T * s)

V(out) = V(int) * K

V(fb) = A * V(out)

Solving this system brings: V(out) / V(in) = GCL = 1 / A * 1 / (1 + T * s / (A * k)) and: V(int) / V(in) = 1 / (A * K) * 1 / (1 + T * s / (A * k))

Closed loop gain is a first order low pass filter with DC gain 1 / A and cutoff frequency A * k / (2 * pi* T)

Signal at integrator output is low pass filtered with the same cutoff frequency as closed loop gain. DC gain from input is 1 / (A * K)

As we can see, many modulator characteristics depend on K, the comparator+DFF gain. How can we estimate that gain? Low frequency signal amplitude at integrator output gives the value:

Ratio of input signal to integrator output is 8.49779 mV / 212.13 mV = 1 / 24.96. This ratio was calculated to be 1 / (A * K). Then A * K # 25. Since A = 2, K = 12.5

There is another approach to understand this relatively small value. Back to previous post (Hands on Sigma Delta modulators part 2), we can see that integrator output contains 80 mVpp of noise. This noise amplitude does not depend on signal amplitude (except if amplitude is zero). If we have a very small signal, DFF output duty cycle will be 50%, the noise having a zero average value. Now, if we add a DC value to the integrator output, DFF output duty cycle will change. If noise average value is negative, DFF output will be more often 0 than 1. If noise average value is positive, DFF output will be more often 1 than 0. If noise average value varies over a range equal to the noise peak to peak value, DFF output duty cycle will vary from 0 to 1. In other words, K is the ratio of output duty cycle change to average integrator output change. K = 1 / Vnpp.

With Vnpp = 80 mV, we find K = 1 / 0.08 = 12.5

Now where does that 80 mVpp noise come from? It comes from the loop activity permanently trying to null the difference between input and feedback through oscillation caused by loop instability as seen in part 1. When input is zero, feedback is positive for 1 clock period and negative for 1 clock period. Integrator output voltage change during clock period is : DV = V(fb) * Tclk / Tau. With the values used in this design, F(fb) = +/- 1 V, Tclk = 400 ns and Tau = 10 us. Peak to peak voltage is the 40 mV. But if input voltage is not zero, integrator accumulates an error and peak to peak value increases until it periodically resets the error. The result is that peak to peak noise is doubled to reach 80 mV, the value we were looking for!

So, integrator output contains signal and triangular noise that can be called "approximation noise". This noise somehow linearizes the comparator+DFF giving it a small signal gain that would not be expected without thinking twice!

All for now.