My Team GaAs Fab Bring Up at Qorvo (TriQuint)

Employed at Bell Labs in Reading Pa, i worked on centering our fab and design, optimizing yield, analyzing data and developing new paradigms for data analytics. Later i was selected to lead our Transfer of our GaAs SARGIC (Self Aligned Refractory Gate IC) HEMT EPI Fab from our fab in Reading to TriQuint, Oregon.

When i started, our yields were terrible, ranging from 0 percent (due to breathing and collapsing, most likely as a result of traps and backgating or side gating). In this mode, charge accumulates in traps and over time, biases the gate region of whatever transistor is near enough. This will cause the operation of the device (in this case, the eye diagram could be seen to breath or collapse, after this DC field built up and biased the gate region) thus the name "Breathing and collapsing".

When devices did work, yield was typically no better than 50%. The reason was said to be the high intra and inter wafer variation.

Packaging costs were high, since they were Ceramic Multi Chip Modules, with Hydrogen getters, so it was very expensive to package marginally bad or broken parts, the cost of GaAs real estate was also high.

Typical GaAs process/design methodology.

PROCESS: Unlike Silicon, GaAs has no algebraic models other than Barrier height. Even that in the SARGIC was empirical since the barrier height was a function of the g rapid thermal anneal that scintered the gate metal to the gate region. Lattice stress also conspired to change properties in the wafer.

SIDE BAR:

I am the sole contributor to the data model creation, SBU turn around. This was because no one thought it could be done. I fulfilled my standard job as Device Wafer Test Engineer which included:

1. Writing 400,000 lines of new code for the Bell Labs Test executive and editing the remaining 200,000 lines to prevent test lock ups and make the software user friendly. Many features added, such as real time Historical data, Variation QQ Normal probablity plots and a custom barchart/yield analyzer (real time) .
2. setup and maintain Shared Resource data and test program server.
3. ISQL relational engineering database setup and CRON loaders, flat file definition for testers. Auto report generation scripts.
4. seting up new HIgh performance RF rack and stack testers, creating RF test rograms for the fiberoptic chip sets.
5. Setup and program custome autoloader probers
6. Create a Hybrid gel pack prober.

DESIGN MODELS: These were generated with Spice type model model extraction software (this was purchased from Cascade Microtech) and used S PArameter testing of FETS, and Structures and included such things as intrinsic and exrinsic GM, RFrds, Anot, Ft and so on, gate capacitance, etc etc. . DC models and were also extracted and included Vt, GM, Sub Threshold, Idd, (square root model of FET cut off), sheet rho and so on.

THE PROBLEM here was the variablity and narrow response surface captured in time, which was subject to move. So it was that devices were designed from models and at a fixed point in time but were produced on a response surface which changed from that point in time where the models were created. In our case, a bit like balancing our fab on the head of a pin. As we used to say about our wafers, "like snowflakes, no two alike, and same for each device inside the wafer.

Now GaAs process has improved, nevertheless, this issue of design models fixed in time versus continuous streaming product remains an issue and so does variability.

I have been fortunate enough to solve this problem at AT&T, Bell Labs and at TriQuint in our transfer. This applied only to our SARGIC line for our AT&T linglines terrestrial and oceanic Fiberoptic chipset, since that was the scope of my work.

When i started, i was responsible for wafer testing of our GaAs chipsets (Laser Driver, CDR, Transimpedance Amplifier, Limiting Amplifier and later, transcievers (including developing worlds first Sonet IP ATE with LTX on a Fusion HF tester (SN 2 Beta) for our early 1.7 Gb/s (worlds first fiber chipset) and subsequent OC48, OC192 (including internal die probe debug), and OC768 (development wafer test 80 GHz).

I discussed with my peers at Bell Labs and AT&T (there were no titles there, everyone, on an engineering level, could discuss issues) this issue of yield loss. I reasoned that the process RF and DC measurements should be sufficient to create real time empiricle models to predict device performance at final test and also as an aid in setting and holding foundry targets, with sensitivity gauges as well. I identified the problems and was informed, yes of course, we know of this and have tried unsuccessfully for years to model it. The reason given, correctly so, i found this in my daily study of all the production data from the birth of the wafer to final test, study of all the yield loss steps, i found the problem was the high inter and intra wafer variation, high orthogonality in the data (with important information in the tails). Of course, data transforms were out of the question due to the orthogonality in the data, so even a data transform would introduce even more variablity, unless a third order benchmark could be found, i saw none.

So i undertook a study of modelling and found that software Neural Network models can tolerate high levels of orthogonality, can model both crossing and non crossing interactions to any level, include non linearity to any level.

I took courses in this, created a relational engineering database of all of our data (i was responsible for our data collection as well) and created a methodology to associate test data with surrounding device sites (one of the reasons i had been given we could not model data was the high variability and so averages dd not work.. so i created spatial relations which tied different data sources together based on their spatial relationship to each other). Thus i created a dataset for training and experimenting from all past manufacturing data going back several years. Next i created my Neural Network model, including second order interactions and non linearity, i did a square root transform on cut off voltage as well and created my training and test data sets.

I created a network that predicted final device performance and, therefore, yield. Since this was historical data, i foreknew the final result.

Next, i plotted the wafer process data in three dimensions versus spatial yield result data and found process targets that produced good yield. As an example, my wafer primary device yield patterns changed from basically scatter shot, to unique patterns such as i called them, smiley faces and ghosties. "Then i laid the good final test spatial data over the process data for each process flow, and found some very amazing results i think, for example, with Idd, the three D plot looked like an upside down row boat (on the wafer) and as i plotted each wafer, i found the slice moving through the distribution and if viewed from the top, i could exactly see the resulting yield patterns at the intermediate device probe and confirmed good at final test. So now i had valid targets for the fab, even though the fab was changing from the model point, i could see in real time where good devices were coming from.

I applied the same correlation technique to device wafer probe using final test data relationally, using spatially related data rather than averages.

So i had my model and was ready in all aspects to deploy it, which i did.

I applied the new wafer tests and limits, i deployed a shell script that printed out final device yield at the wafer process step and waited.

First lost through saw final test yield move from the zero to fifty percent region to NINETY EIGHT percent and it stayed there.

FAB TRANSFER:

When our fab was transferred to TriQuint (three inch to five inch conversion) i was put in charge of the transfer team at AT&T Bell Labs. Another SBU had been chosen to lead the transfer, they tried for almost two years and failed. I toldl our group we must take this from them and run it since our wafer store is almost depleted, was never intended to take this long. Our only salvation was

1. my scripts that predicted yield
2. Our SBU manager David Harrison, who, being a realist, doubled the store before fab shut down (for transfer).

I was able to set the targets, we resolved each one in our transfer meeting with TriQuint Or, with Doctor Brophy on the TriQuint side.

about 90 days later we had our first lot with 98 percent yield.

Now why did i succeed ? because the first SBU was using fixed second level model extractions. They would run a lot, and then test the lot and then reset what they thought they needed to, then another run and more testing.

I did not of that, i extracted to targets from wafers, i based my optimization, not on averages but on individual devices. The high variability was actually a plus here. I set the targets and we ran the first lot and it was good, because i already knew what made a good device from the process data itself.

Our SBU went from being the least profitable at AT&T to being the most profitable, RETURNING $250M on $500M in sales.

LASTLY, with this type of model, i added a slider control panel to the model, which allowed me to see how variations in any process parameter would affect device characteristics and yield.

Now as a postscript, i have been accused of being used to unlimited resources of large companies. Let me say our SBU was small (being the least profitable), many times i had to go to our scrap warehouse ( i knew the operators there very well, who loved to see me come in). This was the place where all the other SBU sent their old equipment to be scrapped, i put a lot of it back into service in our line, since, well, at the time we were the least favorite. Even so, my management trusted me and allowed me to get the training and tools i needed to transform our SBU and i delivered on their trust in me. We had the best people in the world in our SBU, each and every one, i miss that can do skunkworks drive, open minded and dedication where anything dreamed can be realized.