FPGA Latency Arbitrage Tax

Introduction

Thanks to Spencer Dean for pointing me towards the Microstructure Exchange where I came across the paper Quantifying the high-frequency trading “arms race” by Matteo Aquilina , Eric Budish , and Peter O'Neill .

The premise of the paper is the following: Suppose you are a market maker. There will be times when you try to cancel an order but the cancel request reached the exchange too late. Somebody has already traded against your quote. You were latency arb'd. You account for these bad fills by quoting a little wider than you would otherwise be able to do. One can consider this wider spread as a "latency arbitrage tax" imposed on other market participants.

Aquilina et al. used a non-public dataset from the LSE from 2015. They focus on trades which included multiple participants trying to aggress (but some failing) or which included failed cancels (i.e., the scenario described above where the liquidity provider's cancel request came too late). They then calculate the liquidity providers' profitability (i) including all fills and (ii) excluding fills during these competitive events. The difference is the "latency arbitrage tax".

Methodology

Only using public data one can do something very similar for Eurex and Xetra. Instead of relying on misses and late cancels which are not present in the public data, we can identify competitive events based on the winner's reaction time. For the purpose of this article, I use a threshold of 1 μs for the reaction time and consider all trades on Xetra or Eurex as possible triggers. This narrows it down to FPGA-triggered orders - sophisticated HFTs.

More precisely, I extract a list of all passive executions from A7 (including their ExecID - a timestamp). Using the high-precision timestamp files, I then (a) locate the event by matching the ExecID, (b) take the aggressors t_3a timestamp, and (c) find the most recent trade whose t_9d is at least 2720 ns smaller than the aggressors t_3a. The estimated wire-to-wire (w2w) reaction time of the aggressor is w2w = t_3a - t_9d - 2720 ns.

This yields two categories of fills for the liquidity providers: those FPGA-triggered orders and non-FPGA-triggered orders. Let's denote them as HFT and non-HFT. We then calculate the average T+10 s markout of these trades - from the liquidity providers' point of view. And, just as Aquilina et al., we can then compute a "FPGA latency arbitrage tax" by taking the different between the non-HFT markout and the overall markout.

Results

Figure 1 below shows the result for a number of cash equities (constituents of the DAX, MDAX, and SDAX) as well as the most liquid futures (DAX future - FDAX, Euro STOXX50 future - FESX, and the Bund future - FGBL). The "FPGA latency arbitrage tax" is the blue sliver. The annotation is the value and, in brackets, the percentage of the traded notional which falls into the HFT buckets. The grey bars represent the median spread for comparison.

The results are somewhat surprising and, at first glance, implausible. The magnitude is very small - especially relative to the spread. Any possible price improvement in the absence of aggressive HFTs would be tiny compared to the spread to cross. Take the FESX, for example. The "tax" is just 0.03 bps. For additional comparison: the exchange fee is approximately 0.06 bps.

How does this reconcile with the reported profitability of HFT trading (why else invest in FPGAs and everything else required to be latency competitive?). Staying with the FESX. The "tax" on the overall market may be 0.03 bps but since this comes from a bit more than 10% of the volume, then this means that the HFT fills alone are 0.3 bps more profitable than the other trades.

Notes

• The results do not change much when setting the threshold to 10 μs instead of 1 μs.

#hft #marketmaking #equitytrading #equitymarkets #lowlatency #fpga #derivativestrading #futurestrading #ull #microstructure