FLOORPLANNING

Find approx locations of a set of modules that need to be placed on a layout surface.

-Available region typically considered rectangular

-Modules are also typically rectangular in shape

Problem Definition

• Input:

-n blocks with areas A1,A2,....An

-Bounds ri and si on the aspect ratio of block Bi

• Output:

-Coordinates (xi,yi), width wi and height hi for each block such that hi.wi =Ai and ri <=hi/wi <= si

• Objective:

-Minimize area, reduce wire length for critical lengths

Points to note:

• Floorplanning problems is more difficult as compared to placement (Multiple choice for the shape of a block)
• In VLSI design styles, these problems are identical

Design Style Specific Issues

• Full Custom:

-All the steps required for general cells

• Standard Cell:

-Dimensions of all cells are fixed

-Floorplanning problem is simply the placement problem

-For large netlists,two steps:

~first do global partitioning

~next carry out placement for individual regions

• Gate array:

-Floorplanning problems same as placement problems

Estimating cost of a floorplan

• The number of feasible solutions of a floorplanning problem is very large (finding best solution is NP-hard)
• Several criteria used to measure the quantity of floorplans:a)Minimum areab)Minimum total length of wirec)Maximum routabilityd)Minimum delayse)Any combination of above

How to determine area?

-Not difficult

-can be easily estimated because the dimensions of each block is known

-area A computed for each candidate floorplan

How to determine wire length?

-a coarse measure is used

-based on a model where all I/O pins of the blocks are merged and assumed to reside as its center

-overall wiring length L = Zigma (Cij * dij),where Cij - number of connections between blocks i and j, dij - manhattan distances between the centers of rectangles of blocks i and j

DEAD SPACE

The place within a floorplan which is wasted.Minimizing area is same as minimizing deadspace