Five Technical Elements of Wafer Level Packaging

Wafer Level Packaging (WLP) is an advanced packaging technology, which has developed rapidly in recent years because of its advantages such as small size, excellent electrical performance, good heat dissipation, and low cost. According to Verified Market Research research data, the wafer-level packaging market is US$4.84 billion in 2020 and is expected to reach US$22.83 billion by 2028, with a compound annual growth rate of 21.4% from 2021 to 2028.

Different from the traditional packaging process, wafer level packaging is to package the chip while the chip is still on the wafer. The protective layer can be glued to the top or bottom of the wafer, and then the circuit is connected, and then the wafer is cut into individual pieces. chip.

Compared with wire-bond and flip-chip (Flip-Chip) packaging technologies, wafer-level packaging technology can save processes such as metal wires, epitaxial pins (such as QFP), substrates or lead frames, Therefore, it has the advantages of small package size and good electrical performance.

Most of the leaders in the packaging industry mass-produce advanced wafer-level packaging products based on the wafer model. Not only can the existing wafer-level manufacturing equipment be used to complete the operation of the main packaging process, but also the packaging structure and chip layout can be designed in parallel. Become a reality, which in turn significantly shortens the design and production cycle and reduces the overall project cost.

Compared with traditional packaging, wafer-level packaging has the following advantages:

1. Small package size

Because there are no wires, bonding, and plastic processes, the package does not need to expand outside the chip, making the package size of WLP almost equal to the chip size.

2. High transmission speed

Compared with traditional metal lead products, WLP generally has shorter connection lines, and it will perform better under high performance requirements such as high frequency.

3. High density connection

WLP can use array connection, the connection between the chip and the circuit board is not limited to the periphery of the chip, and the connection density per unit area is increased.

4. Short production cycle

In the whole process of WLP from chip manufacturing to packaging to finished products, the intermediate links are greatly reduced, the production efficiency is high, and the cycle is much shortened.

5. Low process cost

WLP completes packaging and testing at the silicon chip level, and achieves the goal of cost minimization through mass production. The cost of WLP depends on the number of qualified chips on each silicon wafer. The development trend of chip design size reduction and silicon wafer size increase reduces the cost of a single device package accordingly. WLP can make full use of wafer manufacturing equipment, and the cost of production facilities is low.

It should be emphasized that, unlike wire-bonded packaging technology, there are multiple options for internal signal routing (Internal Signal Routing) using wafer-level packaging technology for wafer-level packaging: Wafer Bumping (Wafer Bumping) ) technology, Re-Distribution Layer technology, Silicon Interposer technology, Through Silicon Via technology, etc.

Advanced wafer-level packaging technology mainly includes five elements:

① Wafer Bumping technology;

②Fan-In wafer-level packaging technology;

③Fan-Out wafer-level packaging technology;

④2.5D wafer level packaging technology (including IPD);

⑤3D wafer level packaging technology (including IPD).

Wafer bumping (Wafer Bumping), as the name implies, is to form or install solder balls (also known as bumps) on the preset positions of the wafer before cutting the wafer. Wafer bump is the key technology to realize the interconnection between chip and PCB or substrate (Substrate). The material selection, structure, and size design of the bump are affected by many factors, such as package size, cost, and performance requirements such as electrical, mechanical, and heat dissipation.

Printed Bump technology, Ball Drop with Eutectic Plating technology, Lead-Free Alloy and Copper-Pillar Alloy bump technology, fan-in type Wafer-level packaging (Fan-In Wafer Level Package, FIWLP) technology, also known as wafer-level chip scale packaging (Wafer Level Chip Scale Package, WLCSP) technology in the industry, is the main force in various wafer-level packaging technologies today. In the past two years, the global shipments of fan-in wafer-level packaging products have remained at more than 30 billion pieces per year, mainly supplying mobile phones, smart wearables and other portable electronic product markets.

With the shrinking space of portable electronic products, the increasing operating frequency and the diversification of functional requirements, the number of chip input/output (I/O) signal interfaces has increased significantly, and the bump and solder ball pitch (Bump Pitch & Ball The precision requirements of Pitch are gradually becoming stricter, and the mass production yield of redistribution layer (RDL) technology is therefore more and more valued. In this context, high-end wafer-level packaging technologies such as Fan-Out Wafer Level Package (FOWLP) and Hybrid Fan-In/Fan-Out have emerged.

Here we expand and introduce the Re-Distribution Layer (Re-Distribution Layer, RDL) technology. In the wafer-level packaging process, the redistribution layer technology is mainly used to re-plan (also can be understood as optimized) signal wiring and transmission paths between the bare die (Bare Die) and the solder balls, so as to achieve wafer-level packaging The purpose of maximizing the signal interconnection density and overall flexibility of the product. The technical core of RDL is simply to add one or more layers of lateral connections to the original wafer to transmit signals.

The figure below shows a typical Chip-First RDL scheme. Please note that there are two layers of dielectric (Dielectric) materials here to protect the RDL layer wrapped by it (which can be understood as a stress buffer). In addition, the Under Bump Metallurgy (UBM) technology is also used here to help the contact (Contact Pad) support the solder ball, RDL and dielectric.

With the popularity of ultra-high-density multi-chip modules (Multiple Chip Module, MCM) and even system-in-package (SiP) products in 5G, AI, high-performance computing, automotive autonomous driving and other fields, 2.5D and 3D wafer-level packaging technologies Popular with designers. The figure below shows 2.5D (left) and 3D (right) wafer-level packaging technologies.

As shown on the left side of the figure above, for 2.5D wafer-level packaging technology, the signal interconnection of two chips can be realized through redistribution layer (Re-Distribution Layer, RDL) or silicon interposer (Silicon Interposer) technology. As shown on the right side of the figure above, for 3D wafer-level packaging technology, the signal interconnection of logic and communication chips such as CPU, GPU, ASIC, and PHY can also be connected through the redistribution layer (RDL) or silicon interposer (Silicon Interposer). ) technology to achieve. However, the signal interconnection between multiple High-Bandwidth Memory (HBM) chips stacked in 3D and the logic chips at the bottom is realized by Through Silicon Via (TSV) technology. Of course, how to choose between the above types of interconnects requires a case-by-case analysis based on actual specifications and cost targets.

Regardless of whether we focus on the present or the future, with the rush of major technological trends such as 5G, artificial intelligence, and the Internet of Things, wafer-level packaging technology will surely occupy a place in the technical competition of high-density heterogeneous integration.