First-Pass Silicon Success for Synopsys MIPI C-PHY/D-PHY on TSMC N3E

Synopsys MIPI C-PHY/D-PHY RX IP on TSMC N3E silicon is up and running at a blistering 44Gbps! The silicon can receive high resolution image sensor traffic up to 6.5Gsps per trio in C-PHY mode and 6.5Gbps per lane in D-PHY mode, and supports C-PHY v2.0 and D-PHY 2.1. Also check out the Synopsys MIPI C-PHY/D-PHY TX IP with wide-open eye and clear margins on TSMC N3E silicon.

The Synopsys MIPI C-PHY/D-PHY enables essential high-performance, low-power interfaces to SoCs, application processors, and peripheral devices. The PHY offers built-in test capabilities, including pattern generation, logic analysis, and loopback modes covering all circuits. It is part of our complete MIPI solution with seamless interoperability with Synopsys’ ASIL B Ready ISO 26262 certified CSI-2 and DSI/DSI-2 controllers for applications requiring functional safety, such as in automotive cameras.

Summary

Synopsys and TSMC have partnered closely to provide our mutual customers with a broad portfolio of high-quality IP for many generations of TSMC’s processes. We are excited to announce that we have TSMC N3E silicon back and in the lab, and everything is looking strong.

The tapeout included a wide range of IP to help our HPC data center, automotive, consumer and enterprise customers achieve first-pass silicon success on TSMC’s most advanced process technologies:

????????Multi-Protocol 112G PHY x4

????????PCIe 6.0 (64 Gbps) PHY x4; PCIe 5.0 (25GbE) MP32G PHY x4; PCIe 4.0 (16.0 Gbps) PHY x4

????????DDR5 PHY (8.4 Gbps)

????????LPDDR5X/5/4X PHY (8533 Mbps, 9600 Mbps overclocked)

????????USB-C 3.2/DP 1.4 PHY

????????MIPI C-PHY/D-PHY Combo RX 6.5Gbps/6.5Gsps