First-Pass Silicon Success for Synopsys DDR5 PHY on TSMC N3E

Check out the Synopsys DDR5 PHY IP operating at a blazing 8400 Mbps showing a wide-open eye and clear margins on TSMC N3E silicon. First-pass silicon success on the advanced TSMC N3E process enables our customers to develop high-capacity, and high-performance memory solutions with faster time to market and reduced risk.

DDR has become the de facto technology for designers requiring the highest capacity off-chip memory technology. Synopsys DDR5 IP supports JEDEC standard DDR5 SDRAMs and memory modules operating up to 8400Mbps servicing server, enterprise, AI, and networking applications. Synopsys DDR5 IP is part of the complete Synopsys DDR interface solution that includes PHYs, controllers, secure inline memory encryption (IME), IP subsystems, verification IP, and IP Prototyping Kits.?

Summary

Synopsys and TSMC have partnered closely to provide our mutual customers with a broad portfolio of high-quality IP for many generations of TSMC’s processes. We are excited to announce that we have TSMC N3E silicon back and in the lab, and everything is looking strong.

The tapeout included a wide range of IP to help our HPC data center, automotive, consumer and enterprise customers achieve first-pass silicon success on TSMC’s most advanced process technologies:

????????Multi-Protocol 112G PHY x4

????????PCIe 6.0 (64 Gbps) PHY x4; PCIe 5.0 (25GbE) MP32G PHY x4; PCIe 4.0 (16.0 Gbps) PHY x4

????????DDR5 PHY (8.4 Gbps)

????????LPDDR5X/5/4X PHY (8533 Mbps, 9600 Mbps overclocked)

???????USB-C 3.2/DP 1.4 PHY

????????MIPI C-PHY/D-PHY Combo RX 6.5Gsps/6.5Gbps