First 5 years of PULP: Open source hardware for everyone

It has been exactly 5 years since Luca Benini started the PULP (Parallel Ultra Low Power) project in a meeting attended by a handful of people squeezed in a tiny office in the University of Bologna. Next week at the RISC-V workshop in Barcelona, our project will be mentioned in several talks (hopefully all in a good light), not only by members of the PULP team from ETH Zurich and University of Bologna, but from several other groups as well. We are aware of talks and presentations by Embecosm, Dolphin and Google that have used our designs in their projects and products, and who knows maybe there will be even some more [Ed 13.05: indeed at the workshop IBM and NXP made also announcements that they use/evaluate PULP]. Recently, both Greenwaves and CEVA announced products based on PULP. We are very proud that our work is finding applications and recognition in the "real world", and has proven itself to be more than "a toy that academics play with". Of course many research groups also use PULP based systems in their work. Some of these involve us directly, such as the OPRECOMP H2020 project led by IBM Research - Zurich where we are developing systems that are able to adjust the numerical accuracy of their operations in order to save energy both in the IoT and HPC domain. However there are many groups that are able to use our work in their projects independently. This is possible since we share PULP openly with everyone through our GitHub page using a permissive (Apache like) Solderpad License.

Our first release in February 2016 was a RISC-V based 32-bit micro-controller called PULPino written completely in SystemVerilog. We have followed this up, by an area efficient 32-bit RISC-V core that we called zero-riscy, and more recently with a more advanced Linux ready 64-bit RISC-V core Ariane. We have also updated our platform offerings with the 32-bit single-core PULPissimo and the multi-core Open PULP system. Just last week we have released our Virtual Platform for our 32-bit architectures as part of our Software Development Kit, which provides a bit-accurate and timed model of the PULP architecture targeting application development, debugging and profiling. The platform not only simulates the cores but also all the IPs of the architecture: interconnects with latency/contention models, DMA, event unit, accelerators, padframe, timers, serial interfaces and so on. And there is still more to come. Development of all released components continues on public repositories, so everyone has access to the most up to date versions of our code and we are happy to receive comments, suggestions and bug reports on all our releases.

In the 5 years since we launched the PULP Project, we have developed and tested more than 20 ASICs in various technologies. We are expecting our latest chip, Poseidon, in Globalfoundries 22FDX technology back from manufacturing any moment. The HDL code for the PULP based blocks used in this chip is already available for everyone to use on our GitHub page (just to clarify: at the moment licensing restrictions allow us to provide only HDL code), giving everyone who is interested access to silicon proven IP.

There are still many skeptics of the open source hardware movement, and I will not be able to convince everyone that open source hardware has a future. However I can tell you that, as the main PULP development team at ETH Zurich and University of Bologna we are committed to continue to support high-quality open source hardware and we are in discussions on participating several exciting projects that we hope to be able to announce soon. Remember to follow us on twitter (@pulp_platform) to see what we are up to next.