Fault Modeling in DFT?

Fault models are a means of abstractly representing manufacturing defects in the logical model of your design. Each type of testing - functional, IDDQ and at-speed targets a different set of defects.

We will look at a few basic fault models that are relevant to us while trying to form basic concepts around DFT. ?There is a relationship between test types, fault models, and the types of manufacturing defects targeted for detection. The below table shows that relationship:

Below we have details of the relevant fault models:

Stuck-at Fault:?This fault is modelled by assigning a fixed (0 or 1) value to a signal line in the circuit. A signal line is an input or an output of a logic gate or a flip-flop. The most popular forms are the single stuck-at faults, i.e., two faults per line, stuck-at-1 (s-a-1 or sa1) and stuck-at-0 (s-a-0 or sa0)

Transition Fault:?It is assumed that in the fault-free circuit all gates have some nominal delays and that the delay of a single gate has changed. The gate delay, usually an increase over the nominal value, is assumed to be large enough to prevent a passing transition from reaching any output within the clock period, even when the transition propagates through the shortest path. Possible transition faults of a gate are slow-to-rise and slow-to-fall types and hence the total number of transition faults is twice the number of gates.

Path-Delay Fault:?This fault causes the cumulative propagation delay of a combinational path to increase beyond some specified time duration. The combinational path begins at a primary input or a clocked flip-flop, contains a connected chain of logic gates, and ends at a primary output or a clocked flip-flop. The specified time duration can be the duration of the clock period (or phase), or the vector period. Propagation delay is defined for the propagation of a signal transition through the path. Thus, for each combinational path there are two path-delay faults, which correspond to the rising and falling transitions, respectively.

Quiescent Current (IDDQ) Fault:?These faults are relevant to the CMOS technology. In the steady state (i.e., when the gate is not switching) the CMOS logic gate provides no conducting path between the power supply and ground. Thus, the steady state current, also known as the leakage or quiescent (IDDQ ) current, of a CMOS gate is on the order of only a few microamperes. Under various fault conditions in the gate, this current can rise by several orders of magnitude thus allowing fault detection via current measurement. Faults detectable by this method are called IDDQ faults.

Source:

- Mentor and Synopsys ATPG user guides

- CMOS VLSI Design: A Circuits and Systems Perspective by Weste & Harris

- Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits by Bushnell & Agrawal

etc