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Fault analysis – What is Your Real FIT Size?

Mike BARTLEY

SVP at Tessolve Semiconductors Part-time Consultant for Alpinum Consulting and Training

发布日期: 2016年2月15日

Avidan Efody, Verification Architect at Mentor Graphics, recently spoke on the fault de-rating techniques available at various abstraction levels, and explained how they should all be combined to get a realistic estimate of FIT(Failures in Time) numbers and ISO26262 architectural metrics at the Verification Futures Conference on 4 Feb 2016.

The Presentation Slides of “Fault analysis – What is Your Real FIT Size?” are available now

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