External Forces

In the last installment, AppliedMicro had acquired TPACK, bought into a Software Defined Chip? approach, defined a first-pass unified roadmap, and started to roll it out to customers. At that time, the nature of the partnership with the FPGA companies had changed dramatically. While independent, TPACK was an excellent IP and design services partner, who did not represent a threat to its historical partner, Altera. The new perceived threat was from AppliedMicro +TPACK: designs using FPGA-based products to ASSPs in production. This fear had no foundation in fact -- but the perception was absolutely real. From the point of view of the FPGA supplier, they would do all the work of winning a design, only to be replaced in production by an ASSP product from AppliedMicro. From APM/TPACK’s point of view, we would do all the work of winning a design and damned well needed to get an ROI on the Software Defined Chips investments.

There is a history in the industry of going from FPGA to a cost-reduced piece of silicon. The FPGA companies themselves have programs that take a systems customer’s FPGA design and convert it to a lower cost alternative. Altera’s HardCopy and Xilinx’ EasyPath provided such paths. With those programs, the FPGA company retained the design throughout the life of its production at a lower price, when their customers actually exercised the lower cost option. What was even more interesting to me: historically, FPGA customers exercised this lower cost option a lot less than 10% of the time.

The FPGA paranoia ran deep, particularly with the FPGA field sales teams. We had an unfortunate joint conference call with Altera and a customer a few days after the acquisition was announced, where our people unwittingly described the worst case scenario: FPGA prototype followed by ASSP production as our primary business model. Nothing was further from the truth, but the damage had been done. This perceived threat spread like wildfire throughout the Altera sales organization. I found myself doing damage control by making personal calls to multiple sales leaders at Altera, putting a choke-chain on our own marketing and sales teams, writing a very tight script for them, and spending a great deal of time working with my Altera counterpart.

In the case of ASSPs from AppliedMicro, the perceived threat was one of integrating the FPGA functionality with other FPGAs and our own design IP. This meant an entirely new design for the customer, and almost none of them would halt the production revenue of the first Software Defined Chip?. The strong and paranoid feeling of the FPGA guys was that they were a prototype, and we would steal their “rightful” business away. When emotions run high and wide, the problems become more difficult. This condition became a core impediment for us at APM with Altera.

 Leveling the Playing Field

The damage-control approach did not really work until we started quoting both Altera and Xilinx on new designs. Then, things changed. We now felt we had the strength to win designs with very little support from the FPGA supplier. APM was a longstanding and often preferred supplier to our target telecom customer base. We had the resources to back up our claims - something that TPACK, as a standalone company, had lacked. And, to our pleasant surprise, the customer viewed the design content as the #1 factor at the beginning of a new board or system design. The hardware vehicle on which the design resided (Xilinx or Altera or ASSP) only mattered when considerations such as cost and power came into play. These considerations usually came later on advanced designs. Being the first supplier gave us a huge advantage and offering either Xilinx or Altera made our “Switzerland” strategy work.

Game On!

Given this strength, we pursued new pieces of business and told the customer that they could select the FPGA supplier. Suddenly, Xilinx and Altera found themselves competing for new designs, and the threat of being left out of production became secondary. Because of core architectural differences between these two suppliers, porting from one to the other was easier said than done, but TPACK had been extremely disciplined about writing a system spec and then designing in a high level descriptive language (VHDL, followed later by SystemVerilog). From these high level languages, we could synthesize designs that targeted whatever FPGA we chose. It turns out that how we went to market varied depending on the situation. Where we and one of the FPGA guys were the incumbent and the customer wanted a modification or an evolutionary next generation design, we tended to stick together. On new designs or applications, we played Switzerland.

The TPACK team continued to deliver at a steady rate and with a high degree of predictability. It was not magic by any means. By following the systems-definition approach, using SystemVerilog, verifying the designs at a logic level, and doing extensive testing with our evaluation systems, we were able to commit and meet schedules on a very reliable basis. In the folklore of FPGA designs, the number of engineers who hack a design, program it into the FPGA, and then try it out on the fly are legendary. In fact, many systems-company FPGA developers tend to use this approach. While you can push a design out pretty rapidly, it leaves you exposed to bugs, especially out in the field long after the design is released. The re-programmability of FPGAs is both a blessing and a curse. Their ability to very rapidly prototype and bug fix represent a modern wonder. But the lack of disciplined verification often results in failure - which turns into an ugly tale of woe.

One of the stories I love to tell is that, over the four years we were together, there was only one instance of a TPACK schedule slip to a customer commitment. The TPACK team let me know almost a month in advance about it and had a recovery plan fully thought through. I called the customer to flag the problem, got their understanding (and appreciation for the advanced notice), worked out a resolution on the schedule, and in the end strengthened our relationship. You cannot ask for better than this in the semiconductor world, given the complexity and difficulty of high integration designs.

The bottom line: design methodology counts. But the discipline to follow it matters even more. And competition in your partner and supply chain can fundamentally change the way the game is played. Just make sure it is played in your favor…

Next installment: Fundamentals and Economics

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