Exploring TSMC InFO_oS and InFO_PoP certification

By Keith Felton

When it comes to semiconductor packaging, achieving thinner profiles, better performance, and higher integration density has become the gold standard. One of the most widely adopted platforms driving this innovation is Fan-Out Wafer Level Packaging (FOWLP), a technology that has taken the mobile computing world by storm. From smartphones and smartwatches to tablets and laptops, FOWLP has become synonymous with cutting-edge performance. Among the leaders in this space is 台积公司 ’s Integrated Fan-Out (InFO) technology, part of their 3DFabric platform.

InFO technology has two main variants that cater to different use cases: InFO_PoP and InFO_oS. Each brings its own unique strengths to the table, but both share the common goal of pushing the boundaries of semiconductor integration. Let’s take a closer look at these technologies, their design challenges, and the importance of EDA tool certification in ensuring design success.

What is TSMC InFO technology?

TSMC’s Integrated Fan-Out (InFO) technology is a commercial version of FOWLP and is well-known for its ability to enhance performance while reducing the size and thickness of advanced semiconductor packages. It is widely used in mobile computing applications due to its ability to meet the demanding requirements of devices like smartphones and tablets.

Currently, InFO is available in two main variants:

• InFO_PoP (Package-on-Package): This variant integrates a mobile application processor with DRAM memory in a package-on-package assembly. It eliminates the need for an organic package substrate and C4 bumps, resulting in a thinner profile and superior electrical and thermal performance. This makes it ideal for mobile applications where space and efficiency are critical.
• InFO_oS (On-Substrate): Designed for higher-density applications, InFO_oS features advanced 2/2μm RDL (Redistribution Layer) line width/space, enabling the integration of multiple advanced logic chiplets. It is particularly suited for 5G networking applications, offering hybrid I/O pad pitches as small as 40μm. This level of density and performance is essential for next-generation networking and compute-intensive tasks.

The challenges of designing InFO packages

Designing packages using TSMC’s InFO technology is not just an evolution of traditional methods; it is a paradigm shift. Unlike older organic build-up packages, which closely resemble High-Density Interconnect (HDI) PCB technology, InFO packages require entirely new design techniques.

Here are some of the unique challenges:

• InFO packages have stricter design and manufacturing rules compared to traditional organic PCB processes. Designers must adhere to these constraints to ensure manufacturability and performance.
• With 2/2μm RDL line width/space and hybrid I/O pad pitches as low as 40μm, the density of InFO designs far exceeds that of traditional PCB packages.
• The Design Rule Checking (DRC) signoff process for InFO packages is more akin to semiconductor processes than PCB processes. This requires advanced EDA tools capable of handling the intricacies of InFO designs.

To address these challenges, TSMC provides rigorous guidelines for designers and partners with EDA vendors to ensure their tools are up to the task.

The role of EDA tool certification

To maintain a high standard of design quality and manufacturability, TSMC has developed a certification process for EDA tools. This certification provides a consistent and measurable approach to evaluate whether an EDA tool can meet the design needs.

Siemens EDA has recently achieved this certification for Xpedition Package Designer as part of the InFO_oS and InFO_PoP workflows driven by the Innovator3D IC cockpit, which include HyperLynx DRC and Calibre nmDRC.

Find more information here!