End-to-end open source SoC design ready for use in classroom

As part of the PULP Platform team open-source hardware is something that I am very passionate about. For years we were able to deliver high-quality, silicon-proven RTL code on our GitHub page, but we could not share complete designs. For an end-to-end open-source design where you have access to all views of a completed ASIC that is ready for manufacturing, in addition to the source (RTL and simulation environment for a digital design), you need an OpenPDK and Open EDA tools so that every aspect of the design files can be shared openly.

IHP is one of the few companies that provide an OpenPDK for their 130nm technology and thanks to the excellent work of Harald Pretl there is an up to date image that contains a great collection of Open-Source IC tools, providing a path for us to release end-to-end open-source designs. We have already taped out several designs (Iguana, Basilisk) where we progressively increased the use of open-source EDA tools. And now we have MLEM, a design completed by Hannah Pochert and Luisa Wüthrich as part of their semester thesis at our group at ETH Zürich. MLEM is an implementation of our Croc SoC template based around a 32bit RISC-V core (CVE2 which is based on the popular Ibex core).

At ETH Zürich we have a long tradition that provides an environment for students to work on their own ASICs as part of their studies dating back to late 1980s. Starting next year, we will move these lectures to use predominantly open-source tools and the Croc template we used in MLEM will form the basis of the student projects. At the moment there is not much, but we hope to have the lectures and exercises available under vlsi.ethz.ch when we start our lecture in February 2025.

I feel very fortunate to experience the growth of open-source hardware firsthand. From when we first started experimenting with end-to-end open-source IC Design flows, we have seen so much improvement thanks to the great collaborations we have with many contributors. For example only 6 months ago when we taped-out Basilisk, we needed a long chain of tools to convert our SystemVerilog code to Verilog so that Yosys could synthesize the netlist as detailed in our paper at IWLS2024. Thanks to the great work by Martin Povi?er from YosysHQ for MLEM we can now directly read-in our SystemVerilog using the excellent yosys slang plugin. We will continue to collaborate with our friends and colleagues to improve the open-source hardware eco-system.

I am excited about the future of open-source hardware. I believe that especially for teaching and making it easier for more people (and companies) to get their first experience with IC design, end-to-end open-source ASIC flows are really well suited. Now if we can get an open PDK in a technology node in the 65-28nm range, things will become really interesting. Watch this space.