Elevate Your Digital IC Design and Verification Skills: Join Our Affordable Online Courses
Mohammed Zakir Hussain
Assistant Professor at Muffakham Jah College of Engineering & Technology | Senior Member IEEE | IEEE CAS Member | FPGA Design Engineer | ASIC Digital Engineer | Verification Engineer using SV and UVM
Digital IC Design:
Welcome to the course on Digital IC Design, where you'll embark on a comprehensive journey through the essential aspects of designing digital integrated circuits. Over six weeks, this course will equip you with a robust understanding of Verilog HDL, FPGA design, and ASIC design approaches, offering both theoretical knowledge and practical skills. Starting with an in-depth introduction to Verilog HDL, you'll explore the language's intricacies, the critical differences between simulation and synthesis, various modeling styles, and the design of combinational and sequential logic circuits, including FSM design.
Following this, you'll delve into FPGA design methodologies, gaining hands-on experience with industry-standard tools like Intel's Quartus Prime Design and AMD's Vivado. The course will culminate with an exploration of the ASIC design process, guiding you through the RTL-to-GDSII design flow using open-source PDK and the OpenLane EDA tool. This structured progression ensures a holistic understanding, preparing you to tackle real-world digital IC design challenges with confidence and expertise.
SystemVerilog-Based IC Verification:
This course provides a thorough introduction to the key improvements that SystemVerilog brings to the Verilog HDL. SystemVerilog offers significant advantages over Verilog, including its capability to execute constrained stimuli, utilize object-oriented programming (OOPS) features in test-bench construction, and implement functional coverage assertions, among other enhancements. By combining the verification capabilities of Hardware Verification Languages (HVL) with the ease of use of Verilog, SystemVerilog offers a unified platform for both design and verification tasks.
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SystemVerilog brings several improvements to the classic Verilog HDL, making it the preferred option for hardware design and verification. In this internship, we extensively explore the capabilities of SystemVerilog from a verification perspective only, enabling you to construct strong and effective digital systems verification environment.
High-Level Synthesis (HLS) with MyHDL
Digital Integrated Circuit (IC) design has undergone a remarkable transformation with the advent of High-Level Synthesis (HLS). HLS offers a streamlined methodology to convert high-level language descriptions into RTL (Register Transfer Level) designs, significantly reducing design time and enhancing productivity. In this three-week course, we delve into the fundamentals of HLS using MyHDL, a Python-based framework, and explore the synthesis and simulation of RTL designs using open-source tools.