Electromigration and IR Drop - Part 3

IR drop analysis used to be a simple problem on designs implemented in the older technology nodes. The VDD and VSS power grids in such designs are not as dense as is the case in the N7, N5, N3, N2 etc., technology nodes.

Large power grids are very common these days. As a result, analyzing IR drop during implementation (or construction) and during sign-off has become computationally expensive in terms of runtime, memory utilization, and the number of iterations it takes to finally sign-off a design. Also, these large power grids implemented using smaller nanometer technology nodes have to supply power at much smaller operating voltages. Since the designs have thinner wires and high switching circuit density per unit area, a poorly designed power grid can contribute to performance degradation. Most of the IR drop related problems can be caught well ahead using steady state analysis. Hence, analyzing the design for steady state behavior and dynamic (aka temporal) behavior before sign-off is important. For this discussion, I will use steady state analysis for a major part of this discussion as my goal is to introduce how EM and IR problems are solved, generally.

The problem of steady state or DC IR drop analysis neatly fits into the class of problems we can solve using linear system approaches. A point to note is that solving power grid circuits implemented using various dense metal routes using linear solvers can be too challenging. One solution is to naturally solve such grids using iterative solving. These iterative methods are still based on matrix solving methods such as element-to-element or node-to-node, and row-based matrix solving. (Enhanced solvers using Intel MKL, BLAS, LAPACK, and other math libraries can handle large matrices in a computationally efficient way).

Fig 1. shows a steady state representation of the power grid for a single metal layer. Red rectangles are resistors and blue circles are the current drains (switching circuits). Let us assume we just have a power grid of single metal layer type for this discussion. If we solve the power grid for this metal layer in steady state, we can think of voltage sources (in this picture, I used vddsrc_1 and vddsrc_2 to represent such voltage sources) as constant voltage sources. The instances supplied by this grid are modeled as independent current sources because these instances are simply current drains.

In such a case, our power grid problem can be thought of as a linear system of the form:

Ax = b

where,

A is the conductance matrix

x is the vector of node voltages of our power grid and

b is a vector of current sources.

Here is where linearly solving the power grid becomes complicated. Assume we have a matrix A of ’n’ rows and ‘m’ columns. If ’n’ and ‘m’ are large values, then solving such a linear system of equations can be computationally prohibitive. For example, if A is a matrix of 3000 rows and 3000 columns, then we have 9,000,000 elements to handle! Designs implemented in N5, N3, and N2 nodes can have as few as few million to as many as 100 billion or more elements on the power grid. So, naturally various methods are used to solve such large circuits.

Since iterative methods are used in solving power grids, I will state four different types of iterative methods commonly discussed as foundational concepts: Gauss-Seidel method, Successive Over Relaxation method, Group Iterative method, and various Random Walk based methods. Solving large designs fully flat using improved iterative approaches is still not efficient and computationally expensive. This is because for large power grids (think in terms of millions of nodes to billions of nodes), our matrix A is often substantially large and sparse. Hence, hierarchical solutions are preferable.

The main point here is that steady state IR drop analysis can uncover majority of serious IR drop problems early on. You will still have to run dynamic IR drop analysis before sign-off though. At the same time, signing off large designs fully flat is not practical. So, interest in hierarchical sign-off is growing.

Hierarchical analysis solutions are a good choice as long as there is no loss of accuracy. Another approach is to separate the global power grid and local power grids, and then solve them as such. The problem is we end up still encountering computational time and space complexity. Yet another approach is to apply parasitic reduction techniques while extracting the power grid from physical layout. But that too can introduce accuracy loss! If hierarchical IR drop analysis is the choice, then that hierarchical analysis must meet these three basic expectations:

1. Highly accurate for sign-off,
2. Computationally fast and scalable, and
3. Uses significantly less hardware resources.

Further, this hierarchical analysis should interact well with physical design side, sign-off IR aware timing flows, and with system side of the package flows. If you are working with large designs and flat sign-off is not possible due to the large size of your power grid, you should absolutely look at Voltus XM solution. It has consistently showed great results with high accuracy at 5nm, 3nm, and 2nm for muti-billion instance and multi-billion node designs. Also, Voltus Insight is another flow you must absolutely look into as Voltus Insight together with Innovus, Tempus, and Voltus significantly reduces the number of IR drop related problems during sign-off.

I will elaborate more on the foundational algorithms used in power grid analysis and ECO guided design fixing in my upcoming articles.