ECO Implementation Tips, which I learnt from my Physical Design Experience.

In this article, I would like to share with you my ECO (Base & Metal) implementation techniques which I learned over the past few years working in a wide variety of VLSI projects. Starting from an engineer who can't implement basic Ten Gate ECO to now being called as one of the ECO experts in our Industry. Hope the below nuggets of wisdom that I learned burning midnight oils will help you in taking your career in Physical Design to the Next Level.

I would highly suggest people who are in the field of Backend in VLSI not to miss this article.

?Let's get started.

If you are trying to swap a violating net to good net like feedthrough_opt or relay nets which are usually routed in higher metal layers- make sure it won't break the good nets' driver cell ( > 120ps is not recommended as it might further degrade 50 ps after swapping of bad to good net). Always give prority to timing path for good net with good slack margin also. Driver of net , its cell delay and max_transition are most important.

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For bypassing a buffer there is no need to completely remove the buffer we can simply disconnect and connect only that pin of combo cell provided that excluding the combo pin other paths are having positive slack margin. It doesn’t matter if buffer is having high fanout unless we don’t disturb the net shapes already routed by tool

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?Don’t try to place the eco cells close to inputs for saving buffers, you need to check slack margins at all the input pins whether they can be placed far and try to?insert?buffer as they already have good margin and all. Highlight the flylines- Check legality should be done before going to route_exec step. Remove the spare cells once eco cells are used in their place to avoid overlaps in check_legality command.

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When swapping the cells by using custom procedures make sure you check the max_capacitance attribute who knows whether the driver is weak or strong. Simply assuming will not work, and it may degrade the timing further by blindly swapping.

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Only inverters and buffers can be routed in higher layers. Combo cells if weak if upgraded to higher layers, can completely degrade the transition as we have additionally loading the net capacitance b'coz of upgrading to M6 -M10 layers. Strictly not recommended.

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When you place the ECO cells it is strictly recommended that you check the timing through the newly added cells. ICC timing and validation of placement needs to be done properly before going to metal fill

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My suggestion if you want to swap location of a spare cell with existing similar cell for larger distance like 20-30u make sure that old cell which is of no interest if it is having high fanout and whether old cell can drive the fanout after location swapping to larger distance. One Best Practice is try to use any spare buffer in that non critical path just to ensure that transition violations don’t come up.

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In ECO tcl given by RTL owner if he is tweaking SE or SI pins please ensure you run scan check immediately and report back to RTL owner. Any combo logic in SI path is not allowed. Only buffer and inverter are accepted other wise shadowing of flops can't be controlled by DFT team.

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In ECO tcl if RTL owner is tweaking clock pins make sure to see the flylines and if they are Okay or delete those clock related eco lines from the tcl, which is not necessary.

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Timing ran on trim fill cannot be accurate. Always ensure inc_fill for verifying timing results. As it gives the necessary pessimism for max-setup corners.

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Whenever you change or modify the original ECO tcl make sure you run gate to gate Formality and the designs are equal. Analyze one by one failing point which is easier to debug.

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When there are no tracks available for new eco signals and if you want to ask for Power Net "VSS" chops request to IR (Reliability verification) team check the IR drop is Okay to chop the particular metal segment or not. But this is not recommended unless there are no other options available.

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When highout fanout nets are to be improved always consider logic duplication. Try to find spare buffer or inverter nearby if not found try to swap with near by (<30u ) inverter cells which has good slack margin and then try to split the load. Load splitting should be done according to the placement. Blindly dividing the load into two halves won't work in Metal ECOs.

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when "VDD" tie-off command is to be used we need GNAC diode to be used we can't leave the power net floating.

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If there are?hold?violations in Metal eco, there is no option than using whatever spare buffer are present in near vicinity. One more option is try to ask Physical verification engineer whether he can route some net segments in lower layers if we are having good setup margin just to ensure that net delay is increased for meeting?hold timing.

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A flop cannot drive more than 10u, don’t take risk by placing the load of flop too far. Also combo cells can't drive more than 45u provided it is double height and low vth cells. Otherwise don’t place more than 30u distance. These are Best Practices for placing the eco cells for 10nm,7nm technology nodes.

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Always try to see if there are any buffers in the net fanout so that we can tap the buffer output net so that we can save buffer?insertion?unnecessarily.

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Any combo cell more than 3 input pins are very weak drivers care should be taken that they are placed close to their loads.

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Whenever any new buffer is?inserted?try to give net routing rule min M6 to max M10 constraints otherwise tool will place in lower layers degrading the timing again.

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set_cell_location is compulsory in case you want to control the placement of new ECO cells. Highly recommended.

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Remove any redundant buffers or inverter pair in the timing path, before removal see the net delay values visually in GUI.

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Logic restructuring is one of the complex ECO fixing technique. Always ensure when you are bypassing any combo cell ( pin swapping ) fanin and fanout are not more than "One". Otherwise, the Formality might fail. Try to draw the boolean equation and ensure that bypassing is done properly or not.

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If a net is having a load of 5 and one cell is floating then disconnecting that cell and decreasing the load to 4 also helps in slack improvement. One of the Best known methods for fixing tricky violations.

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Always using low vt cells over high vt cells will give good slack margins and help in timing. For cell swaps also try to use low vt cells if present in the vicinity of the area of interest.

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If we want to decrease the delay of a spare cells like AOI cell or OAI cell which are high delay cells and these were used in place of nor or nand gates due to unavailability of spare gates for nor or nand gates. We can search nearby nor or nand gate and completely disconnect the i/p and o/p pins and connect the driver cells output ( This is same as cell location swapping but it is useful for swapping different ref_names like OAI cell ( 3 i/p) and NOR cell (2 i/p). Best known method if used for swapping different ref_names. ( connect_pin command is used here )

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For any noise violations always ask for PV team suggestions whether is the availability of tracks so that we can add shielding nets instead of adding buffer.

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If you don’t know the significance of any script ask two to three people and try to understand. Don't blindly implement Metal ECOs without understanding scripts and usage properly

Always make sure you see the net profiles of bad nets and try to improve by using custom procs.

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For metal ECO for every manual eco flow ensure that PDS XOR is being run in PV domain and ensure base XOR is clean. Very important.

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If Muxes are used in ECO tcl with one i/p grounded try to replace it with nob cell ( a!b) as Muxes take huge delay compared to nob cell which is relatively two i/p simple combo gate.

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When you are bypassing any buffer in metal eco, don’t check whether buffer is present in webreport paths ( by search technique) even though the endpoint is same. Even pins of same registers can have different paths. Always ensure by excluding the buffer in prime time session. This is very important. Don’t take webreports as worst endpoints. Only PT session gives the correct analysis for Block owners.

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Some times pin capacitance of combo cells?will be different for different inputs. Try to swaps the input pin connections according to small pin capacitance as it takes lesser time to charge the node. Useful in Metal ECO implementation.

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For shorts reduction in ECO mode always downsize the large cells so that space is created. It is indirectly like setting a keep-out margin. Also, go to the short marker ( in yellow color ) if the neighboring cells are clumped try to move slightly so that gap is created between the cells.

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We can see any unwanted Diode cells in particular bbox ( get_cells -within {} ) and remove these cells for creating more space. ( short reduction technique in ECO mode )

?If there are any top level port created in ECO tcl ask for incremental DEF with Floorplan team. If any port is not properly connected to the corresponding partition Formality may pass but Full chip Formality will fail. Please be careful. Port punching should be done properly. Or else in ICC optimization it may ground any floating nets in the design.

Finally, I want to wrap up the article with the below words of the famous Charlie Munger.

"Wisdom acquisition is a moral duty. It’s not something you do just to advance in life. As a corollary to that proposition which is very important, it means that you are hooked for lifetime learning. And without lifetime learning, you people are not going to do very well. You are not going to get very far in life based on what you already know. You’re going to advance in life by what you learn after you leave here.?"

Thank you very much. We are done for now.

Regards

Sriharsha Pudi

Lead Engineer @SpicaWorks