DVCon Functional Safety

DVCon Functional Safety

At DVCon last week, there was an update on the Accellera Functional Safety Standard that is in development. The working group (WG) is chaired by my Cadence colleague Allessandra Nardi. Also on the presentation were:

  • Vatsa Prahailada, who is Technical Director at NXP San Diego (and previously was at?Intel and Qualcomm)
  • Darren Galpin, who is Principal Digital Verification Engineer at Renesas UK, working automotive power devices (and previously at Infineon Bristol and ST Microelectronics)

Darren is also Secretary of IEEE Functional Safety Standards Committee. The expectation for the Accellera standard is that, like other earlier standards, it will be developed in Accellera, go through a period of shakeout for a year or two, and then be submitted to become an IEEE standard. Which, I guess, means it will land on Darren's desk in, say, 2025. There is already an IEEE standard number, IEEE P2851 (the P means provisional, so in progress and not a standard yet).

If you need to get up to speed on functional safety (FS or sometimes FuSa), then I've written plenty of Breakfast Bytes posts about it. Work your way through:

Alessandra opened by saying that the presentation would be an update on the Accellera standard that the working group is developing. The group was formed two years ago. Last?May, it published a white paper with the very vanilla name of?Functional Safety Working Group: White Paper. The WG is working on a second white paper on the data model, originally scheduled for literally right now, but is slipping out into Q2.

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