DRAM memory chip

The DRAM market has experienced a roller coaster ride over the past year or so, from oversupply to undersupply, and then to the final balance of supply and demand, and the financial reports of manufacturers have also been on a roller coaster ride.

According to Yole's research report, the storage industry is currently recovering at a faster rate than previously predicted, and revenue is expected to soar in 2024 and 2025. After DRAM revenue increased to US$98 billion in 2024 (an increase of 88% year-on-year), revenue is expected to continue to grow to a record high in 2025, and the DRAM market is expected to reach US$137 billion. Driven by strong demand growth (especially in the data center field), the DRAM market is expected to continue to grow to US$130 billion in 2029, with a compound annual growth rate of about 17% from 23 to 29.

The good news is that the market is returning to normal, and the bad news is that manufacturers are about to start again. As the market gradually returns to normal, each company has tried its best to gain more market share. Even in the case that the DRAM market has been fought to only three giants - Samsung, SK Hynix and Micron, the competition is still very fierce.

For the semiconductor industry, technology always comes first. Whoever can achieve technological leadership can transform this advantage into the market, and the same is true for products such as DRAM.

Among them, Samsung and SK Hynix have commercialized products based on 1a and 1b chip designs, including DDR5, LPDDR4X, LPDDR5 and LPDDR5X, and their DRAM chips are designed to the smallest 12nm level. The two companies are in the lead in adopting EUV lithography, while Micron continues to use ArF and ArFi lithography technology to 1α and 1β generations, and plans to introduce EUV in 1γ generation. Samsung expanded EUV lithography to more than five layers of masks in 1a and 1b generations. SK Hynix has also adopted a similar strategy and plans to add EUVL steps in the future.

Regarding the hottest HBM technology, although all three manufacturers have officially announced HBM3E, Samsung is the first manufacturer to announce and mass produce 12-layer HBM3E, while SK Hynix will mass produce 12-layer HBM3E in the third quarter of this year, and Micron will complete mass production of the product in the second half of the year.

As for how these three manufacturers perform in DRAM technology, let's take a look at a more detailed interpretation.

EUV

"Although (the semiconductor market situation) is not very good, it is only at this time that we can truly show our strength." In January 2019, Samsung Electronics Chairman Lee Jae-yong answered this question when asked about the semiconductor market situation after the "2019 Entrepreneur Dialogue".

SK Group Chairman Choi Tae-won, who heard this answer nearby, said: "Samsung's words are the most frightening."

The "real strength" mentioned by Lee Jae-yong implies the strong strength of Samsung Electronics, which has maintained the first position in the global DRAM market since the 1990s.

In December 1992, Samsung won the first place in the global DRAM market for the first time, and has never given up this position since then. It can be said that DRAM is the thickest root system of Samsung Electronics, which continuously supplies nutrients to this towering tree. A senior official of Samsung Electronics' DS (semiconductor) department said: "Traditionally, there is an unwritten rule that 'genius engineers must go to the DRAM development team', and the team leaders who lead DRAM development and design are all geniuses among geniuses."

The reason why Samsung DRAM is unique in the world is simple, that is, it has achieved a far leading position in miniaturization process technology. The importance of DRAM miniaturization is that it directly affects product performance. As the circuit line width decreases, the integration of DRAM increases, thereby improving performance and power efficiency. This means that electronic devices respond faster and consume less battery. In addition, as the number of semiconductors that can be manufactured from a single wafer increases, production efficiency is also improved.

DRAM miniaturization has gradually evolved from 30 nanometers and 20 nanometers to 10 nanometers, and Samsung Electronics has always had an overwhelming advantage in this process. 10-nanometer DRAM is produced in the order of 1x (first generation) -1y (second generation) -1z (third generation) -1a (fourth generation) -1b (fifth generation). Samsung announced as early as the first quarter of 2016 that it would take the lead in mass production of the 10-nanometer 1x process, while SK Hynix and Micron started mass production almost a whole year later. From 10-nanometer 1x to 1z, Samsung is undoubtedly the first, and has formed a crushing trend against the other two in terms of technology and market.

But the variables appeared in the fourth generation. In January 2021, Micron announced that it would be the first to mass produce 10nm-class fourth-generation (1a) DRAM, changing the situation in which Samsung had absolute dominance in the past. As DRAM enters the 10nm process, the difficulty of miniaturization technology has increased significantly. The miniaturization process that was previously promoted by improving argon fluoride (ArF) lithography equipment has reached its limit. Starting from 2022, it is generally believed that the DRAM technology of Samsung, SK Hynix and Micron is essentially on the same level. At this stage when argon fluoride equipment has reached its limit, extreme ultraviolet (EUV) lithography equipment has come on stage. As the next-generation semiconductor production equipment that uses extreme ultraviolet light to engrave ultra-fine circuits on chips, it is seen as an alternative to break through the technical limitations of existing equipment. In the 10nm fourth-generation development process, Samsung and SK Hynix took the lead in introducing EUV lithography technology, while Micron's approach is slightly different. It uses the "multi-patterning" technology of traditional lithography equipment to perform multiple fine circuit engravings, thereby achieving a faster miniaturization process conversion. Although this method does not require a complete change of the existing method, it will also bring about problems such as an increase in process steps and a decrease in production efficiency due to the need to etch the circuit multiple times.

The reason why Samsung Electronics slowed down the conversion of the miniaturization process at the 10-nanometer fourth generation was analyzed to be the result of a combination of factors such as the bureaucratization of the R&D organization and trial and error in the EUV process conversion. A senior official of Samsung Electronics explained: "When the miniaturization process entered the 10-nanometer level, the complexity of chip design and production increased, and management seemed too complacent in obtaining the next-generation technology. In particular, EUV equipment took a long time to optimize DRAM production."

In 2024, the key to DRAM technology competition lies in the 10-nanometer fifth-generation (1b) process, and Samsung, SK Hynix and Micron started mass production of products of this process almost at the same time. The circuit line width of the 1b process is only 12 nanometers, and it is also used for the latest HBM3E. According to the process roadmaps of Samsung, SK Hynix and Micron and data from global investment bank UBS, the three companies plan to significantly increase the production of 10-nanometer fifth-generation DRAM from the first half of this year.

Semiconductor industry insiders believe that the "real battle" of DRAM technology competition among the three companies has not yet begun. In particular, the key to winning or losing is to stably apply EUV equipment, which is more difficult to process, to the DRAM process to improve performance and production efficiency. EUV lithography equipment is used in the initial 10-nanometer and smaller fifth-generation (1b) DRAM production processes. Applying EUV equipment to the DRAM process can reduce complex production steps and improve efficiency.

Samsung Electronics and SK Hynix's equipment investment direction this year is to transform to the cutting-edge process of DRAM. As the artificial intelligence (AI) boom has driven the increase in demand for HBM and large-capacity DDR5, it has become urgent to expand the production of cutting-edge DRAM. According to Ebest Investment Securities, in the fourth quarter of this year, 1b DRAM is expected to account for 13% and 11% of Samsung Electronics and SK Hynix's overall DRAM production, respectively.

In 2021, Samsung Electronics took the lead in the industry to apply EUV lithography equipment to DRAM production processes, and it is estimated that it has invested hundreds of billions of won and used at least 30 EUV equipment for production processes. Samsung is expected to accelerate its transition to cutting-edge processes starting this year, as it applied EUV lithography equipment to DRAM earlier than its competitors and experienced trial and error.

SK Hynix has also installed 6 to 7 EUV equipment at its Icheon plant and is stabilizing DRAM mass production. SK Hynix plans to expand the production ratio of 10nm fourth-generation and fifth-generation processes to more than half of total DRAM production by the end of this year. Although the scale of equipment investment is limited, it will focus on promoting the transition to cutting-edge processes in order to expand the production of high-value-added products such as DDR5 and HBM3E (fifth generation), which are expected to have strong demand.

Micron is the last DRAM manufacturer to adopt EUV equipment. It has used DUV instead of EUV for both the fourth-generation and fifth-generation 10nm DRAMs. Micron only announced the introduction of EUV lithography technology in its Hiroshima plant last year. This year, it said that the trial production of 1γ (i.e., the sixth-generation 1C) DRAM using EUV lithography technology is progressing smoothly and is expected to achieve mass production in 2025.

According to Korean media reports, Lee Byung-hoon, a professor at the Department of Electronic and Electrical Engineering at Pohang University of Science and Technology, said: "Future competitiveness in the DRAM market will be determined by the EUV process introduced in DRAM mass production. With the complexity of DRAM circuit design and structure and the miniaturization of processes, the importance of EUV processes is increasing. Companies that can quickly introduce and effectively utilize EUV lithography equipment will dominate the DRAM market."

In addition to the introduction of EUV technology, high-K metal gate (HKMG) technology is also becoming more common. Samsung first used HKMG in the peripheral structure of 1x GDDR6 chips and expanded it to 1y DDR5 chips. Micron implemented HKMG in 1z graphic DRAM and plans to expand it to all DRAM types starting from the 1β generation. SK Hynix adopted HKMG in 1y and 1a GDDR6 and recently used this technology in 1b DDR5 devices.

It is expected that by the beginning of next year, the three major manufacturers will mass-produce 1c DRAM, and then launch the final 10nm DRAM product (1d or 1δ node) in 2026 or 2027. By 2030, DRAM technology is expected to shrink to single-digit nanometer nodes, covering several generations of products such as 0a, 0b, 0c or 0α, 0β, 0γ. For now, Samsung is focusing on developing VS-CAT and VCT 3D DRAM, while SK Hynix and Micron are focusing on vertically stacked DRAM.

HBM

HBM is undoubtedly the hottest DRAM technology and product in the past year or so, with Samsung, SK Hynix and Micron engaging in a "three-kingdom war" around it.

SK Hynix has become the leader in this industry and is constantly consolidating its leadership in this niche market. This year alone, SK Hynix has invested 1.3 trillion won in advanced packaging facilities in South Korea to increase its ability to produce high-end chips, and according to Goldman Sachs, the company accounted for 54% of the HBM market last year. Starting from the third generation, Hynix has taken the lead in equipping its HBM with the so-called MR-MUF (reflow molding bottom fill) packaging technology, which involves injecting liquefied protective materials between stacked chips to protect the device and prevent heat dissipation. It is considered to be the core driving force behind SK Hynix's current dominance in this field.

Hynix said that when developing the third-generation HBM product, HBM2E, it took heat transfer control as the main focus of improvement. Even though TC-NCF technology is recognized as a packaging solution for densely stacked products, SK Hynix continues to challenge the status quo and finally launched a new packaging technology MR-MUF in 2019.

It mentioned that MR-MUF technology was jointly developed by multiple teams of SK Hynix. This technology can heat and interconnect all vertically stacked chips in HBM products at the same time, which is more efficient than TC-NCF technology that fills thin film materials after stacking chips. In addition, compared with TC-NCF technology, MR-MUF technology can increase the number of thermal dummy bumps for effective heat dissipation by four times.

In contrast, Samsung's choice of TC NCF (non-conductive film hot pressing) is slightly different from MR-MUF. Each time it stacks chips, a layer of non-conductive adhesive film is placed between the layers. The film is a polymer material used to isolate chips from each other and protect the connection points from impact. The advantage of this method is that it can minimize the warping that may occur as the number of layers increases and the thickness of the chip decreases, making it more suitable for building higher stacks. ”

It is worth mentioning that another important feature of MR-MUF technology is the use of a protective material called epoxy molding compound (EMC) to fill the gaps between chips. EMC is a thermosetting polymer with excellent mechanical, electrical insulation and heat resistance, which can meet the needs of high environmental reliability and chip warpage control. Due to the application of MR-MUF technology, the heat dissipation performance of HBM2E is 36% higher than that of the previous generation HBM2.

In order to maintain the overall thickness of the product, DRAM chips must be 40% thinner than the chips used in 8-layer HBM3, so solving chip warping becomes a key issue. SK Hynix has developed a more advanced MR-MUF technology for this purpose, and introduced the industry's first chip control technology (Chip Control Technology) and a new protective material to improve heat dissipation. In the process, the new EMC used in the advanced MR-MUF technology improves the heat dissipation performance by 1.6 times compared with the EMC in the original MR-MUF technology.

After talking about Hynix, let's talk about Micron. Micron, which was still lagging behind last year, has achieved a curve overtaking this year, breaking the dual-hero pattern of Samsung Electronics and SK Hynix and officially joining the competition. Since the second quarter of this year, Micron has begun to provide a small amount of HBM to its largest customer, Nvidia, thus forming a situation of three strong competition.

It is reported that SK Hynix is the first of the three companies to pass Nvidia's quality test (Qual Test) and has become Nvidia's main supplier. The industry estimates that SK Hynix's HBM3E yield has entered a stable stage, and its operating profit margin is about twice that of DRAM.

However, SK Hynix still faces challenges in expanding its HBM3E production capacity in the short term. People familiar with the matter revealed that although Nvidia continues to pressure SK Hynix to increase supply, SK Hynix needs to produce the existing HBM3 (fourth-generation HBM) in addition to HBM3E, so its available production capacity has actually reached its limit.

On the other hand, although Micron has begun to supply Nvidia, it can only supply a small amount due to yield issues. According to the details of Micron's financial report, the company has supplied Nvidia with HBM3E products worth about US$100 million in the past three months, and considering the unit price of HBM3E, this supply is not considered a large-scale supply.

The industry speculates that Micron has also encountered difficulties in yield. According to Micron's public information, the operating profit margin of the HBM business is lower than that of DRAM. Typically, HBM costs 2-3 times more than DRAM, which means Micron has not yet achieved ideal profitability in its HBM business.

The source said: "Considering that Micron confidently mentioned that it will mass-produce and supply HBM3E next year, it is expected that the supply of HBM3E will not increase significantly this year. Nvidia must speed up the quality certification of Samsung Electronics' HBM3E and obtain supply to meet the sales demand of AI accelerators."

Samsung is obviously lagging behind the above two manufacturers. Its supply of HBM3E to Nvidia has been delayed. The reason is simple. The world's first 36GB 12-layer HBM3E product it developed has not passed Nvidia's quality test so far. It is reported that HBM quality certification usually requires more than 1,000 hours of testing. After passing the test, the two parties will enter the formal contract procedure.

It is said that although Samsung Electronics' HBM3E product is the industry's first product to achieve a 12-layer structure, it has not yet reached Nvidia's standards in terms of performance and energy efficiency. Rumor has it that Nvidia has asked Samsung Electronics to modify some of the HBM3E designs, and Samsung Electronics has also invested a large number of design and process personnel to solve this problem. If Samsung Electronics' HBM3E 12-layer product is approved by Nvidia, the HBM business is expected to be on track in the second half of this year to the first half of next year.

It is also worth noting that SK Hynix and Micron have already used the fifth-generation 10nm (12nm) or 1b process, but Samsung is still quite dependent on the fourth-generation 10nm (14nm) or 1a process, which is likely to be one of the main reasons why it has not been able to solve the HBM heat dissipation problem.

In addition to the above-mentioned improvements in existing manufacturing processes and packaging technologies, hybrid bonding has also become a focus in the HBM battlefield.

According to industry insiders, SK Hynix is developing HBM4 products planned for mass production next year, and uses two different bonding methods: the existing "MR-MUF" (mass reflow-molding underfill) and hybrid bonding technology.

Bonding refers to the bonding process between semiconductors. HBM is a product made by stacking DRAMs, while the MR-MUF bonding method is a process of injecting a viscous liquid between chips to harden them after heating them for a similar operation to welding, while performing a "molding" process for the chip protective shell. In this process, DRAMs are connected by a material called "bumps" (spherical conductive protrusions). Hybrid bonding technology, on the other hand, directly connects DRAMs without bumps. This technology can significantly reduce the thickness of HBM and shorten the distance between DRAMs, thereby speeding up data transmission. Since this technology makes up for the shortcomings of existing bonding methods, it has received great attention from major customers.

A person in the semiconductor industry said: "Due to the high technical difficulty of hybrid bonding, SK Hynix may continue to use MR-MUF in HBM4's 16-layer products, but it is expected that SK Hynix will introduce hybrid bonding technology anyway from the year after next."

It should be noted that the International Semiconductor Standardization Organization (JEDEC) recently relaxed the thickness standard of HBM4 from 720 microns (?) of the previous generation to 775 microns. According to this standard, memory companies have more room to use existing bonding methods to manufacture HBM4. This means that MR-MUF and hybrid bonding technologies may coexist for some time to come.

Compared with Hynix, which is currently in the upper hand, Samsung, which is in a weaker position, has shown a strong desire to successfully apply hybrid bonding technology on HBM4. Industry insiders said: "If hybrid bonding technology encounters difficulties, Samsung Electronics may switch from the current 'TC-NCF' (thermal compression-non-conductive film) method to MR-MUF, but they seem to be more inclined to vigorously promote hybrid bonding."

Samsung believes that hybrid bonding technology is indispensable in HBM products with more than 16 layers. They expressed this position in a paper published at the recent Electronic Components Technology Conference (ECTC) held in Denver, Colorado, USA. Samsung Electronics hopes to become a market leader by being the first to successfully implement hybrid bonding technology without being affected by the relaxation of JEDEC thickness standards.

This may also prompt SK Hynix to speed up the development of hybrid bonding technology to cope with the catch-up from Samsung Electronics. SK Group Chairman Choi Tae-won visited SK Hynix's headquarters in Icheon earlier this month and conveyed to employees the message that "the sixth-generation HBM will be commercialized as early as next year." Industry insiders believe that this statement also includes hybrid bonding technology. In fact, SK Hynix's senior executives frequently mentioned hybrid bonding packaging technology in public.

Meanwhile, Micron, the third largest memory market player, is also conducting research on hybrid bonding technology for HBM4. However, industry observers believe that Micron's technology in this area is relatively less mature than Samsung Electronics and SK Hynix. Industry insiders said: "Micron may continue to use the current TC-NCF process for some time to come."

Attention

In addition to the traditional three major companies, there are also other small and medium-sized enterprises that are working on new DRAM technologies.

At present, the scale and complexity of large language models (LLMs) are growing, and such models require different amounts of memory to store their parameters. Their demand for high bandwidth is increasing, but there is a clear gap in the high-bandwidth but low-density market.

PieceMakers, a fabless company specializing in DRAM, recently launched a new HBLL RAM to fill this market gap. The name "HBLL RAM" stands for high bandwidth, low latency and random access. Compared with HBM, HBLL RAM has two additional advantages: low latency and random access capabilities. This innovation meets the needs of AI applications and provides a combination of low density and high bandwidth.

The HBLL RAM generation currently in mass production provides a low density of 0.5GB and a bandwidth of 128GB per second. Future products are being designed using stacking technology to further improve performance. Strategies include increasing data rates in the vertical direction and expanding I/O width in the horizontal direction. Similar to HBM, HBLL RAM uses 512 I/Os and 1K I/Os for data transmission, and future products will further increase the frequency.

When comparing HBLL RAM to HBM, its advantages are obvious. At the same density, HBLL RAM provides higher bandwidth. Conversely, at the same bandwidth, it provides lower density. This improvement is quantified by the bandwidth density index, which measures the maximum bandwidth per unit density (GB). HBLL RAM significantly outperforms HBM, low-power DDR, and GDDR on this metric.

In terms of energy efficiency, HBLL RAM provides higher power efficiency due to its innovative low-density architecture. This architecture was first debuted at ISSCC in 2017. A single HBLL RAM chip provides 128GB per second of bandwidth through eight channels, with all signal bumps located on one side of the chip. The design results in about half the latency of traditional DRAM and excellent performance in random access bandwidth.

In an article, well-known industry analyst Jim Handy highlighted the potential of HBLL RAM, showing its role between the third-level cache and DRAM. In fact, simulation results using HBLL RAM as a L4 cache are impressive: latency is halved and average bandwidth is significantly improved.

Another advantage is the simplicity of the memory controller, which PieceMakers provides directly to customers. The interface of HBLL RAM is simple and SRAM-like, involving only read and write operations, refresh, and mode register settings. PieceMakers' demo board and customer's circuit board show this innovation using an ABF-only design without CoWos (chip-on-wafer-on-substrate) technology. CoWos is an advanced packaging technology that can cost 2 to 3 times more than traditional flip-chip packaging. Looking ahead, PieceMakers plans to stack HBLL RAM in a similar way to HBM, but without CoWos. This 2D stacking method is expected to further reduce costs compared to 2.5D packaging.

In addition to HBM, more innovations are emerging in the traditional DRAM field. PieceMakers

NEO Semiconductor, a developer of 3D NAND flash memory and 3D DRAM, announced its latest 3D X-AI chip technology in August this year, which aims to replace existing DRAM chips within high-bandwidth memory (HBM) by implementing AI processing in 3D DRAM to solve the data bus bottleneck problem.

NEO said that AI chips using NEO 3D X-AI technology can achieve significant performance acceleration and power reduction, achieving 8 times memory density, and can reduce the large amount of data transferred between HBM and GPU during AI workloads

"Current AI chips waste a lot of performance and power consumption due to inefficient architecture and technology." said Andy Hsu, founder and CEO of NEO Semiconductor. "The current AI chip architecture stores data in HBM and relies on the GPU to perform all calculations. This separated data storage and data processing architecture makes the data bus an inevitable performance bottleneck. Transmitting large amounts of data through the data bus results in limited performance and very high power consumption. 3D X-AI can perform AI processing in each HBM chip. This can greatly reduce the data transmitted between HBM and GPU, thereby improving performance and significantly reducing power consumption."

It is understood that a single 3D X-AI chip contains 300 layers of 3D DRAM cells with a capacity of 128 Gb, and a layer of neural circuits containing 8,000 neurons. According to NEO estimates, each chip can support up to 10 TB/s of AI processing throughput. Using 12 3D X-AI chips stacked with HBM packages can achieve a processing throughput of 120 TB/s, thereby increasing performance by 100 times.

Jay Kramer, president of Network Storage Advisors, said: "The application of 3D X-AI technology can accelerate the development of emerging AI use cases and promote the emergence of new use cases. Using 3D X-AI technology to create the next generation of optimized AI chips will open a new era of innovation for AI applications."

The innovations of the above two companies in DRAM are just a glimpse of the current technological development. As AI applications continue to be popular, more companies will propose their own solutions in the future, which is expected to become an alternative route for DRAM technology.

In the past few years, the once dominant market leader for 20 to 30 years seems to have lost its former glory. Intel has experienced the largest layoffs and stock price plunge in history, while Samsung has struggled with HBM and is no longer leading in DRAM miniaturization technology.

In sharp contrast to them are other manufacturers, especially Nvidia and Hynix. The former has achieved a market value of 3 trillion US dollars by relying on AI, while the latter has reaped rich rewards after years of dedicated operation of HBM.

At present, Samsung seems to have learned from its mistakes and put all its energy back into DRAM. No matter whether it is the miniaturization process or HBM, it cannot afford to lose. Hynix has taken the initiative in technology and market. It has been ranked second for many years and wants to taste the first place. As for Micron, although it has performed quite strongly in the past two years, it may take a long time to catch up with Korean manufacturers due to misjudgment on HMC in the past few years and the slow introduction of EUV technology.

Who can stand out in this battle? Let's wait and see.

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