Difference between if..else and case statement in VHDL

If..else:-

An if…else statement is a sequential statement in VHDL which got executed depending on the value of the condition.

The if condition tests each condition sequentially until the true condition is found. An if..else statement could also be treated as decision making statement and the statement associated with it could be either a Boolean expression or a condition.

It should contain one if statement,can have zero or more else if but at least one else condition,although optional.

The syntax in VHDL is :-

if boolean-expression/condition then 
 sequential statement 
{elsif boolean-expression/condition then 
 sequential statement} 
{else 
 sequential statement} 

end if; 

Let's took a simple example of MUX and it's hardware through which the difference can be drawn with the Case statement.

VHDL code of Mux using if else:-

library IEEE; 
use IEEE.STD_LOGIC_1164.all; 
 
entity 4_1_mux is 
port(X: in STD_LOGIC_VECTOR(3 downto 0); 
     S0,S1: in STD_LOGIC; 
     Z: out STD_LOGIC); 
end 4_1_mux 
 
architecture behav of 4_1_mux is 
 begin 
  MUX : process(X,S0,S1) 
  begin 
   if (S0 = '0' and S1 = '0') then 
    Z <= X(0); 
   elsif (S0 = '0' and S1 = '1') then 
    Z <= X(1); 
   elsif (S0 = '1' and S1 = '0') then 
    Z <= X(2); 
   else 
    Z <= X(3); 
   end if; 

end process; 
end behav;

Now let's look how the hardware structure of if else will look like after synthesis:-

So this clearly implies in case of a if else statement the type of hardware that it is going to produce is a Priority Encoded logic or a Priority block structure.

Case statement:-

A case statement is like a switch construct in C which selects a particular branch among many based on the value of expression.

The syntax for case in VHDL is:-case expression is  when alternative1 => sequential stmnts  [when others => sequential statements] 

case expression is 
 when alternative1 => sequential stmnts 

 
 [when others => Sequential statements]
  endcase

Let's look at code of 4:1 Mux using Case now:-

library declaration and entity part will remain same as if else:-

case {S0,S1} is 
when "00" => Z:= X(0); 
when "01" => Z:= X(1); 
when "10" => Z:= X(2); 
when "11" => Z:= X(3); 
when others => Z:= 'X' // don't care 

endcase

Let's look at the hardware structure of the same mux what case will generate:-

So after synthesis the hardware that is going to generate for case is a MUX and not a priority logic unlike if else.

Some other difference between if else and case are as follows:-

1] On the basis of Optimization and Speed:-

When the number of conditions are more it's a better practice to use Case statement since the compiler will automatically generates a Jump table or a hash table kind of structure from where the data can be fetched which optimised for speed and size.Also the hardware logic in case of CASE will use less resources as comparison to if else.

2] On the basis of readability:-

Case offers compact way of writing a code which offers simple way of readability as compared to ladder like structure of if else.

3] Multi-way branching and Expression:-

Case is useful in case of multi branching statements and if else is more useful for Boolean expression.