Developing a VVC Using the UVVM VVC Generator

With UVVM, we have made it easy and efficient for developers to create structured and robust testbenches. This can be achieved by using the UVVM utility library, which includes checkers, logging, alert systems, randomisation, scoreboarding, and functional coverage, or by utilising a wide selection of BFMs (Bus Functional Models) that enable easy communication with the DUT over a given interface. For those who want to elevate their testbenches to a whole new level, we also offer VVCs (VHDL Verification Components), allowing developers to create even more advanced and structured test setups.

UVVM comes with a range of VIPs (Verification IPs) that support various interfaces: Avalon Memory Mapped, Avalon Stream, AXI, AXI-Lite, AXI-Stream, Ethernet, GMII, GPIO, I2C, RGMII, SBI (Simple Bus Interface), SPI, UART, and Wishbone. These VIPs enable developers to integrate and test a wide range of communication systems in their testbenches.

Although UVVM has a good selection of VIPs, developers sometimes need a VIP that supports a different interface. To assist these developers, we have created vvc_generator.py, a Python script that generates the files and much of the code that is needed to create a VIP for a new interface. In this article, I will describe the steps of generating a VVC using the script, explaining each part of the user interaction and the resulting output.

Running the VVC Generator

The VVC generator script is located inside uvvm_vvc_framework/script/vvc_generator folder, and run the script from the command line with the following command to generate a VVC:

python vvc_generator.py        

Step-by-Step Interaction

VVC Name:

The script prompts you to enter a name for the VVC.

Please enter the VVC Name (e.g. SBI, UART, axilite): i2c        

Extended UVVM Features:

Next, the script offers an option to include extended UVVM features, such as Scoreboard and transaction information, which provide enhanced verification capabilities.

Generate VVC with extended UVVM features? [y/n]: y        

Scoreboard Addition:

Adding a scoreboard helps in automatically comparing the expected and actual outputs of the DUT, ensuring the correctness of the design. The VVCs will automatically set up the scoreboard, making them available immediately in the testbench.

Add scoreboard to VVC? [y/n]: y        

Transaction Info:

Registers the VVC in the UVVM global transaction info register, which opens up for even more UVVM functionality, such as completion detection:

Add transaction info to VVC? [y/n]: y        

Concurrent Channels:

You can specify the number of concurrent channels the VVC will use. Concurrent channels allow the VVC to handle multiple operations simultaneously, which is essential for protocols that operate on multiple channels concurrently (e.g., RX and TX in UART).

Set the number of concurrent channels to use [1-99], press enter for default(1): 1        

Multiple Executors:

Executors manage the execution of commands. Multiple executors are useful for handling concurrent command operations, such as in protocols where commands and responses may overlap.

Shall the VVC have multiple executors? [y/n]: n        

After these prompts, the script generates the necessary files and places them in the output folder.

Generated Files

The script produces several VHDL files based on the provided inputs. These files serve as a starting point for your VVC:

• <name>_bfm_pkg.vhd: Contains BFM methods, configuration records and types.
• <name>_vvc.vhd:The main VVC file, which includes the VVC logic.
• vvc_cmd_pkg: Contains the VVC command record and defaults.
• vvc_methods_pkg.vhd: Includes VVC method implementation examples.
• vvc_context.vhd: Includes library and use clauses in a single context declaration.
• vvc_sb_pkg.vhd: Contains the VVC dedicated Scoreboard.
• vvc_transaction_pkg.vhd: Contains the VVC operations record and transaction info.

Modifying the Generated Files

After the script has generated the files, you will need to customise them to fit your specific BFM and protocol requirements. Search for --<USER_INPUT> markers in the generated code, which indicate where modifications are required.

Conclusion

The UVVM VVC Generator provides an efficient and user-friendly way to create VVCs for UVVM. By automating much of the setup process, it allows developers to focus on customising and extending their VVCs to meet their verification needs.

Inventas is proud to develop and offer UVVM as a free open-source verification tool for FPGA developers. We also develop HDLRegression and recommend developers to use this regression tool to get an even more efficient verification process.

https://github.com/UVVM/UVVM

https://github.com/HDLUtils/hdlregression

#FPGA #ASIC Inventas #Embedded #UVVM #Verification