Demonstration illustrating Non-Equivalence Debug through Pattern Back-Annotation

Debugging non-equivalence can indeed be a challenging task, with potential causes including missing constraint setup, unmatched input end-points, incorrect gate types, or misconnections. This video demonstrates effective techniques to simplify and streamline the process of non-equivalence debugging, making it easier and more efficient.

The fundamental approach involves conducting logic equivalence checking on individual points, significantly enhancing the processing speed. In instances where the result is non-equivalent, a counter-example pattern is generated for the logic analyzed in the LEC. On the schematic, the pattern values are annotated next to the gate pins. Users have the ability to control schematic tracing by specifically clicking on the relevant pins, especially those with differing pattern values.